GW Instek MFG-2000 Series User Manual

REMOTE INTERFACE
381
The Status Byte Register
Description
The Status Byte register consolidates the status
events of all the status registers. The Status Byte
register can be read with the *STB? query or a
serial poll and can be cleared with the *CLS
command.
Clearing the events in any of the status registers
will clear the corresponding bit in the Status Byte
register.
Notes
The Status byte enable register is cleared when the
*SRE 0 command is used.
The Status Byte Condition register is cleared when
the *CLS command is used.
Bit Summary
Register
Bit
Bit Weight
Error Queue
2
4
Questionable Data
3
8
Message Available
4
16
Standard Event
5
32
Master Summary /
Request Service
6
64
Status Bits
Error Queue
There are error message(s) waiting
in the error queue.
Questionable
data
The Questionable bit is set when
an “enabled” questionable event
has occurred.
Message
Available
The Message Available bit is set
when there is outstanding data in
the Output Queue. Reading all
messages in the output queue will
clear the message available bit.

GW Instek MFG-2000 Series Specifications

General

Brand	GW Instek
Model	MFG-2000 Series
Category	Inverter
Language	English