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Intel S7000FC4UR - Chinese Power Supply Cordsets

Intel S7000FC4UR
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Table of Contents Intel® Server System S7000FC4UR
Revision 1.0
x
17.4.2 Supported Wake Events ...................................................................................... 201
17.5 Non-Maskable Interrupt (NMI) Handling .............................................................. 202
18. BIOS Role in Server Management...................................................................................204
18.1 IPMI .....................................................................................................................204
18.2 Console Redirection ............................................................................................ 204
18.2.1 Keystroke Mappings ............................................................................................ 205
18.2.2 Interface to Server Management ......................................................................... 206
18.3 IPMI Serial Interface ............................................................................................ 206
18.3.1 Channel Access Modes ....................................................................................... 206
18.3.2 Interaction with BIOS Console Redirection.......................................................... 206
18.3.3 Serial Over LAN................................................................................................... 207
18.4 Wired For Management (WFM) ........................................................................... 208
18.4.1 PXE BIOS Support .............................................................................................. 208
18.5 System Management BIOS (SMBIOS) ................................................................ 208
18.5.1 Access Methods .................................................................................................. 209
18.5.2 OEM Modification ................................................................................................210
18.5.3 SMBIOS Stuctures Supported ............................................................................. 210
18.6 Security................................................................................................................ 220
18.6.1 Password ............................................................................................................. 220
18.6.2 Password Clear Jumper ......................................................................................221
18.7 BMC Timestamp Synchronization ....................................................................... 221
19. BIOS Error Handling ........................................................................................................223
19.1 Fault Resilient Booting......................................................................................... 223
19.1.1 BSP POST Failure (FRB-2) ................................................................................. 223
19.1.2 Operating System Load Failure (OS Boot Timer)................................................ 223
19.1.3 Operating System Watchdog Failure................................................................... 224
19.1.4 Boot Event ........................................................................................................... 224
19.2 Error Handling and Logging................................................................................. 224
19.2.1 Runtime Error Handler......................................................................................... 224
19.2.2 Error Sources and Types..................................................................................... 225
19.2.3 System Event Logging (SEL) Format Conventions ............................................. 228
19.2.4 IPMI Sensor Type Events — Memory.................................................................. 230
19.2.5 IPMI Sensor Type Events — System Firmware Progress ................................... 231
19.2.6 IPMI Sensor Type Events — Event Logging Disabled......................................... 232
19.2.7 IPMI Sensor Type Events — Critical Interrupt ..................................................... 233

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