Intel S7000FC4UR - North American Power Supply Cordsets

Intel® Server System S7000FC4UR Table of Contents
Revision 1.0
vii
10.2.8 I
2
C Devices ............................................................................................................88
10.2.9 Power Supply Module LED indicators ................................................................... 89
10.3 Regulatory Agency Requirements ......................................................................... 89
11. Power Distribution Board..................................................................................................90
11.1.1 Remote On/Off (-PS_ON)...................................................................................... 90
11.1.2 POWER GOOD SIGNAL (POK, or P_GOOD)....................................................... 90
11.1.3 VIN_GOOD............................................................................................................ 91
12. Front Panel I/O and Control Boards .................................................................................92
12.1 Architectural Overview........................................................................................... 92
12.2 Functional Architecture .......................................................................................... 93
12.2.1 VGA ....................................................................................................................... 93
12.2.2 USB ....................................................................................................................... 93
12.2.3 FRU ....................................................................................................................... 93
12.2.4 Thermal Sensor ..................................................................................................... 93
12.2.5 50-pin Control Panel Connector ............................................................................93
12.2.6 Speaker ................................................................................................................. 93
12.2.7 NMI Button............................................................................................................. 93
12.2.8 Main Board and SAS Backplane Connectors ........................................................ 93
12.3 Front Panel Control Module................................................................................... 94
12.3.1 System ID Buttons and LEDs ................................................................................ 94
13. Basic Input/Output System (BIOS) ...................................................................................96
13.1 BIOS Architecture .................................................................................................. 96
13.1.1 Data Structure Descriptions................................................................................... 96
13.2 BIOS Identification String....................................................................................... 96
14. BIOS Initialization...............................................................................................................98
14.1 Processors............................................................................................................. 98
14.1.1 Multiple Processor Initialization ............................................................................. 98
14.1.2 Processor Built-In Self Test (BIST)........................................................................ 98
14.1.3 Processor Cache ................................................................................................... 98
14.1.4 Microcode Update.................................................................................................. 99
14.1.5 Enhanced Intel SpeedStep
®
Technology............................................................... 99
14.1.6 Thermal Monitor Technology ................................................................................. 99
14.1.7 Intel
®
Extended Memory 64 Technology (Intel
®
EM64T) .......................................99
14.1.8 Execute Disable Bit Feature ................................................................................ 100
14.1.9 Enhanced Halt State (C1E) .................................................................................100