Maxim Integrated MAX32660 - Table 10-1: Timer Register Offsets, Names, Access and Descriptions; Table 10-2: Timer Count Registers; Table 10-3: Timer Compare Registers

MAX32660 User Guide
Maxim Integrated Page 122 of 195
10.12 Timer Registers
Each timer is controlled by a block of registers assigned to that specific timer. All timers contain an identical set of registers.
Register names for a specific instance are defined by appending the instance number to the peripheral name. For example,
the Timer Count Register for Timer 0 is TMR0_CNT while the Timer Count Register for Timer 1 is TMR1_CNT, and so on. The
MAX32660 includes three timer instances, TMR0, TMR1 and TMR2.
The base address for TMR0, TMR1 and TMR2 are as follows:
• TMR0: 0x4001 0000
• TMR1: 0x4001 1000
• TMR2: 0x4001 2000
Refer to Table 3-1: APB Peripheral Base Address Map for the addresses of all APB mapped peripherals.
Table 10-1: Timer Register Offsets, Names, Access and Descriptions
Offset
Register Name
Access
Description
[0x0000]
TMRn_CNT
R/W
Timer Counter Register
[0x0004]
TMRn_CMP
R/W
Timer Compare Register
[0x0008]
TMRn_PWM
R/W
Timer PWM Register
[0x000C]
TMRn_INT
R/W
Timer Interrupt Register
[0x0010]
TMRn_CN
R/W
Timer Control Register
10.12.1 Timer Register Details
Table 10-2: Timer Count Registers
Timer Count Register
TMRn_CNT
[0x0000]
Bits
Name
Access
Reset
Description
31:0
count
R/W
0
Count
The current count value for the timer. This field increments as the timer counts.
Reads to this register are always valid. In general, disable the timer by clearing bit
TMRn_CN.ten, prior to writing the TMRn_CNT field.
Table 10-3: Timer Compare Registers
Timer Compare Register
TMRn_CMP
[0x0004]
Bits
Name
Access
Reset
Description
31:0
compare
R/W
0
Timer Compare Value
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The compare field meaning is determined by the specific mode of the timer. Refer to
detailed configuration section for compare usage and meaning.