MAX32660 User Guide
Maxim Integrated Page 163 of 195
13.3.4 Three and Four Wire SPI Configuration
Select three-wire SPI or four-wire SPI communication using the SPI0_CTRL2.three_wire bit. Set SPI0_CTRL2.three_wire = 0
for four-wire mode or set this bit to 1 to select three-wire operation.
13.3.5 SPI Peripheral Clock
The System Peripheral Clock, PCLK, drives the SPI0 peripheral clock. The SPI0 provides an internal clock, SPI0_CLK, that is
used within the SPI peripheral for the base clock to control the module and generate the SCK clock when in master mode.
Set the SPI0 internal clock using the field SPI0_CLK_CFG.scale as shown in Equation 13-1. Valid settings for
SPI0_CLK_CFG.scale are 0 to 8, allowing a divisor of 1 to 256.
Equation 13-1: SPI Peripheral Clock
13.3.6 Master Mode Serial Clock Generation
In master and multi-master mode the SCK clock is generated by the master. The SPI0 provides control for both the high
time and low time of the SCK clock. This control allows setting the high and low times for the SCK to duty cycles other than
50% if required. The SCK clock uses the SPI peripheral clock as a base value and the high and low values are a count of the
number of
clocks. Figure 13-4, below, visually represents the use of the SPI0_CLK_CFG.hi and SPI0_CLK_CFG.low
fields. Refer to Equation 13-2 and Equation 13-3 for calculating the SCK high and low time from the hi and low field values.
Figure 13-4: SCK Clock Rate Control
Equation 13-2: SCK High Time
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