Maxim Integrated MAX32660 - Table 4-23: Event Enable Register; Table 4-24: Revision Register; Table 4-25: System Status Interrupt Enable Register; Table 4-26: System Initialization Registers, Offsets and Descriptions

MAX32660 User Guide
Maxim Integrated Page 44 of 195
Table 4-23: Event Enable Register
Event Enable Register
GCR_EVTEN
[0x004C]
Bits
Name
Access
Reset
Description
31:2
-
RO
-
Reserved for Future Use
Do not modify this field.
1
rx_evt
R/W
0
RX Event Enabled
Set this field to 1 to enable generation of an RXEV event to wake the CPU from a Wait
for Event (WFE) sleep state.
0: RX Event is disable.
1: RX Event is enabled.
0
dmaevent
R/W
0
DMA CTZ Event Wake-Up Enable
When set, when a DMA block transfer is completed and the DMA counter
DMAn_CNT.cnt = 0, a CTZ DMA event occurs which generates an RXEV to wake-up the
device from a low power mode entered with a WFE instruction.
Table 4-24: Revision Register
Revision Register
GCR_REV
[0x0050]
Bits
Name
Access
Reset
Description
31:16
-
RO
-
Reserved for Future Use
Do not modify this field.
15:0
revision
RO
N/A
Maxim Integrated Chip Revision
This field reads the chip revision id (A1), ascii encoded.
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Table 4-25: System Status Interrupt Enable Register
System Status Interrupt Enable
GCR_SYS_IE
[0x0054]
Bits
Name
Access
Reset
Description
31:1
-
RO
-
Reserved for Future Use
Do not modify this field.
0
iceulie
R/W
0
Arm ICE Unlocked Interrupt Enable
Set this bit to enable a PWRSEQ IRQ if the Arm ICE is unlocked.
0: Interrupt disabled
1: Interrupt enabled
4.12 System Initialization Registers
The SIR base peripheral address is 0x4000 0400. Refer to Table 3-1: APB Peripheral Base Address Map for the addresses of
all APB mapped peripherals.
Table 4-26: System Initialization Registers, Offsets and Descriptions
Offset
Register Name
Access
Description
[0x0000]
SIR_STAT
RO
System Initialization Status Register
[0x0004]
SIR_ADDR_ER
RO
System Initialization Address Error Register