Maxim Integrated MAX32660 - Table 6-8: GPIO Port 0 Registers; Table 6-9: GPIO Alternate Function 0 Select Register

MAX32660 User Guide
Maxim Integrated Page 63 of 195
Enable low power mode wakeup (SLEEP, DEEPSLEEP and BACKUP) from an external GPIO event by completing the following
steps:
1. Set the polarity (rising or falling edge) by writing to the GPIO0_INT_POL[pin] field. The wakeup functionality uses
rising and falling edge detection circuitry that operates asynchronously and does not require an active clock. Dual-
edge mode is also an option to accomplish edge detection wakeup.
2. Clear pending interrupt flags by writing 0xFF to the GPIO0_INT_FL register.
3. Activate the GPIO wakeup function by writing 1 to GPIO0_WAKE_EN[pin].
4. Configure the power manager to use the GPIO as a wakeup source by writing to the appropriate Global Control
register (GCR).
6.5 GPIO Registers
The GPIO0 base peripheral address is 0x4000 8000. Refer to Table 3-1: APB Peripheral Base Address Map for the addresses
of all APB mapped peripherals.
Table 6-8: GPIO Port 0 Registers
Offset
Register Name
Access
Description
[0x0000]
GPIO0_AF0_SEL
R/W
I/O and Alternate Function 1 Select Register
[0x000C]
GPIO0_OUT_EN
R/W
Output Enable Register
[0x0018]
GPIO0_OUT
R/W
Output Register
[0x0024]
GPIO0_IN
RO
Input Register
[0x0028]
GPIO0_INT_MODE
R/W
Interrupt Mode Register
[0x002C]
GPIO0_INT_POL
R/W
Interrupt Polarity Select Register
[0x0034]
GPIO0_INT_EN
R/W
Interrupt Enable Register
[0x0040]
GPIO0_INT_FL
R/W1C
Interrupt Flag Register
[0x004C]
GPIO0_WAKE_EN
R/W
Wakeup Enable Register
[0x005C]
GPIO0_INT_DUAL_EDGE
R/W
Dual Edge Select Interrupt Register
[0x0060]
GPIO0_PULL_EN
R/W
Input Pullup/Pulldown Select Register
[0x0068]
GPIO0_AF1_SEL
R/W
Alternate Function 2/3 Select Register
[0x00A8]
GPIO0_INHYS_EN
R/W
Input Hysteresis Enable Register
[0x00AC]
GPIO0_SR_SEL
R/W
Slew Rate Select Register
[0x00B0]
GPIO0_DS0_SEL
R/W
Drive Strength Select 0 Register
[0x00B4]
GPIO0_DS1_SEL
R/W
Drive Strength Select 1 Register
[0x00B8]
GPIO_PULL_SEL
R/W
Pullup/Pulldown Enable Register
6.5.1 GPIO Register Details
Table 6-9: GPIO Alternate Function 0 Select Register
GPIO Alternate Function 0 Select Register
GPIO0_AF0_SEL
[0x0000]
Bits
Name
Access
Reset
Description
31:14
-
R/W
1
Reserved for Future Use
Do not modify this field.