Table 8-1, above, shows the DIV result for each of the UARTn_BAUD0.clkdiv field settings. With the Clock Divider set to 8 or
16, the resulting DIV value is greater than 1. Setting the clock divider to 16 will generate the most accurate target bit rate
because it is the largest value that results in DIV ≥ 1. Using 16 for Clock Divider, UARTn_BAUD0.clkdiv = 3),
UARTn_BAUD0.ibaud is 1, which is the integer portion of the 1.628 DIV calculation. The UARTn_BAUD1.dbaud field
calculation based on UARTn_BAUD0.clkdiv = 3, UARTn_BAUD0.ibaud = 1 and DIV = 1.628 is:
Equation 8-4: UART dbaud Example Calculation
The resulting field settings for the example 1,843,200 bps rate are:
UARTn_BAUD0.clkdiv = 3
UARTn_BAUD0.ibaud = 1
UARTn_BAUD1.dbaud = 80
8.5 UART DMA Using the TX and RX FIFOs
Each UART has a 32-byte TX FIFO with a dedicated DMA channel and a 32-byte RX FIFO with a dedicated DMA channel. The
DMA channels are configured using the DMA Configuration Register, UARTn_DMA. The RX FIFO DMA channel and TX FIFO
DMA channels operate independently, and each can be enabled or disabled individually. Enable the RX FIFO DMA channel
by setting UARTn_DMA.rxdma_en to 1 and enable the TX FIFO DMA channel by setting the UARTn_DMA.txdma_en to 1.
DMA transfers are automatically triggered based on the number of bytes in the RX or TX FIFO as described in the following
two sections.
8.5.1 RX FIFO DMA Operation
UARTn_DMA.rxdma_lvl configures the number of entries in the RX FIFO that triggers a DMA transfer from the RX FIFO to
system RAM. If the number of entries in the RX FIFO is more than the configured value, a DMA transfer is triggered from the
RX FIFO to system RAM. If UARTn_DMA.rxdma_lvl=0 then a transfer is triggered when there is one byte in the FIFO.
Note: The RX DMA level must be set to a value less than 32 to avoid an RX FIFO overrun condition that results in loss of
received data.
8.5.2 TX FIFO DMA Operation
UARTn_DMA.txdma_lvl sets the number of entries (level) in the TX FIFO that will trigger a DMA transfer from system RAM
to the TX FIFO. If the number of entries (level) in the TX FIFO falls below this value a TX DMA transfer is automatically
triggered from System RAM to the TX FIFO.
Note: The TX DMA level must be set to a value greater than 1 to avoid stalling the UART transfer.
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