Maxim Integrated MAX32660 - Table 14-5: SPIMSS Register Offsets, Access and Descriptions; Table 14-6. SPIMSS Data Register; Table 14-7: SPIMSS Control Register

MAX32660 User Guide
Maxim Integrated Page 189 of 195
Table 14-5: SPIMSS Register Offsets, Access and Descriptions
Offset
Register Name
Access
Description
[0x0000]
SPIMSS_DATA
R/W
SPIMSS Data Register
[0x0004]
SPIMSS_CTRL
R/W
SPIMSS Control Register
[0x0008]
SPIMSS_INT_FL
R/W
SPIMSS Interrupt Flag Register
[0x000C]
SPIMSS_MODE
R/W
SPIMSS Mode Register
[0x0014]
SPIMSS_BRG
R/W
SPIMSS Bit Rate Register
[0x0018]
SPIMSS_DMA
R/W
SPIMSS DMA Register
[0x001C]
SPIMSS_I2S_CTRL
R/W
SPIMSS I
2
S Control Register
14.8.1 SPIMSS Register Details
Table 14-6. SPIMSS Data Register
SPIMSS Data Register
SPIMSS_DATA
[0x0000]
Bits
Name
Access
Reset
Description
31:16
-
R/W
0
Reserved for Future Use
Do not modify this field.
15:0
data
R/W
0
SPIMSS Data
Refer to the SPI Data Movement section for details.
Table 14-7: SPIMSS Control Register
SPIMSS Control Register
SPIMSS_CTRL
[0x0004]
Bits
Name
Access
Reset
Description
31:8
-
R/W
0
Reserved for Future Use
Do not modify this field.
7
irqe
R/W
0
Interrupt Request Enable
Set to enable interrupts for the SPIMSS peripheral.
0: SPIMSS (SPI1/I
2
S) interrupts are disabled.
1: SPI MSS (SPI1/I
2
S) interrupts are enabled. Interrupt requests are sent to the
Interrupt Controller
Note that if transmit or receive DMA is enabled, the transmit data complete
interrupt is disabled, but other interrupt sources are available.
6
str
R/W
0
Start SPI Interrupt
Setting this bit starts a SPIMSS interrupt request. Setting this bit also sets
SPIMSS_INT_FL.irq to 1. Setting this bit forces the SPIMSS to send an interrupt
request to the Interrupt Controller if SPIMSS_CTRL.irqe = 1. This bit is cleared by
writing a 0 to this bit or by writing a 1 to SPIMSS_INT_FL.irq.
5
birq
R/W
0
Bit Rate Generator Timer Interrupt Request
Enable or disable the Bit Rate Generator if the SPIMSS is enabled
(SPIMSS_CTRL.enable = 1).
0: Clearing this bit disables the Bit Rate Generation timer function.
1: Setting this bit to 1 enables the Bit Rate Generation timer function and
enables the time-out interrupt.
Note: If SPIMSS_CTRL.enable = 0, this bit has no effect.