Maxim Integrated MAX32660 - Table 9-3: RTC Sub-Seconds Counter Register; Table 9-4: RTC Sub-Seconds Counter Register; Table 9-5: RTC Sub-Second Alarm Register; Table 9-6: RTC Control Register

MAX32660 User Guide
Maxim Integrated Page 101 of 195
Table 9-3: RTC Sub-Seconds Counter Register
RTC Sub-Seconds Counter Register
RTC_SSEC
[0x04]
Bits
Name
Access
Reset
Description
31:8
-
R/W
0
Reserved for Future Use
Do not modify this field.
7:0
rtss
R/W
-
Sub-Seconds Counter
This field represents sub-seconds and increments at 256Hz. When this field rolls from
0xFF to 0x00, the RTC_SEC.count increments.
Table 9-4: RTC Sub-Seconds Counter Register
RTC Alarm Time-of-Day Register
RTC_RAS
[0x08]
Bits
Name
Access
Reset
Description
31:20
-
R/W
0
Reserved for Future Use
Do not modify this field.
19:0
ras
R/W
0
Time-of-Day Alarm
Sets the time-of-day alarm from 1 second up to 12-days. When this field matches
RTC_SEC[19:0], an RTC system interrupt is generated.
Table 9-5: RTC Sub-Second Alarm Register
RTC Sub-Second Alarm Register
RTC_RSSA
[0x0C]
Bits
Name
Access
Reset
Description
31:0
rssa
R/W
0
Sub-second Alarm
Sets the starting value for the sub-second alarm. The sub-second alarm increments
at 256Hz providing an alarm interval of up to 16,777,216 seconds in increments of
3.9 msec. An alarm is generated when the counter rolls from 0xFFFF FFFF to 0x0000
0000.
Table 9-6: RTC Control Register
RTC Control Register
RTC_CTRL
[0x10]
Bits
Name
Access
Reset
Description
31:16
-
R/W
0
Reserved for Future Use
Do not modify this field.
15
write_en
R/W
0
Write Enable
Set this field to 1 to write to the RTC_TRIM register, the RTC enable
(RTC_CTRL.enable) bit, or both.
1: Writes to the RTC_TRIM register and the RTC_CTRL.enable bit are allowed.
0: Writes to the RTC_TRIM register and the RTC_CTRL.enable bit are ignored.
14:13
-
R/W
0
Reserved for Future Use
Do not modify this field.