Maxim Integrated MAX32660 - Table 4-18: Memory Clock Control Register

MAX32660 User Guide
Maxim Integrated Page 40 of 195
Peripheral Clocks Disable 0 Register
GCR_PCLK_DIS0
[0x0024]
Bits
Name
Access
Reset
Description
9
uart0d
R/W
0
UART0 Clock Disable
Setting this field disables the APB clock to this peripheral. When the clock is disabled, the
peripheral power consumption is reduced, and the peripheral is disabled. Disabling the

Write 1 to disable, set to 0 to enable.
0: Peripheral Enabled
1: Peripheral Disabled
8
-
R/W
0
Reserved for Future Use
Do not modify this field.
7
spi1d
R/W
0
SPI1 Clock Disable
Setting this field disables the APB clock to this peripheral. When the clock is disabled, the
peripheral power consumption is reduced, and the peripheral is disabled. Disabling the
clock to the peripheral does not affect the 
Write 1 to disable, set to 0 to enable.
0: Peripheral Enabled
1: Peripheral Disabled
6
spi0d
R/W
0
SPI0 Clock Disable
Setting this field disables the APB clock to this peripheral. When the clock is disabled, the
peripheral power consumption is reduced, and the peripheral is disabled. Disabling the

Write 1 to disable, set to 0 to enable.
0: Peripheral Enabled
1: Peripheral Disabled
5
dmad
R/W
0
Standard DMA Clock Disable
Setting this field disables the APB clock to this peripheral. When the clock is disabled, the
peripheral power consumption is reduced, and the peripheral is disabled. Disabling the

Write 1 to disable, set to 0 to enable.
0: Peripheral Enabled
1: Peripheral Disabled
4:1
-
R/W
0
Reserved for Future Use
Do not modify this field.
0
gpio0d
R/W
0
GPIO0 Port and Pad Logic Clock Disable
Write 1 to disable, set to 0 to enable. Disabling the GPIO Port and Pad Logic gates off the
clock from the GPIO Port and the individual GPIO pads.
0: Peripheral Enabled
1: Peripheral Disabled
Table 4-18: Memory Clock Control Register
Memory Clock Control Register
GCR_MEM_CTRL
[0x0028]
Bits
Name
Access
Reset
Description
31:13
-
R/W
0
Reserved for Future Use
Do not modify this field.