Maxim Integrated MAX32660 - Table 13-14: SPI Interrupt Enable Registers

MAX32660 User Guide
Maxim Integrated Page 176 of 195
Table 13-14: SPI Interrupt Enable Registers
SPI Interrupt Enable Register
SPI0_INT_EN
[0x0024]
Bits
Name
Access
Reset
Description
31:16
-
R/W
0
Reserved for Future Use
Do not modify this field.
15
rx_und
R/W
0
RX FIFO Underrun Interrupt Enable
0: Interrupt is disabled
1: Interrupt is enabled
14
rx_ovr
R/W
0
RX FIFO Overrun Interrupt Enable
0: Interrupt is disabled
1: Interrupt is enabled
13
tx_und
R/W
0
TX FIFO Underrun Interrupt Enable
0: Interrupt is disabled
1: Interrupt is enabled
12
tx_ovr
R/W
0
TX FIFO Overrun Interrupt Enable
0: Interrupt is disabled
1: Interrupt is enabled
11
m_done
R/W
0
Master Data Transmission Done Interrupt Enable
0: Interrupt is disabled
1: Interrupt is enabled
10
-
R/W
0
Reserved for Future Use
Do not modify this field.
9
abort
R/W
0
Slave Mode Abort Detected Interrupt Enable
0: Interrupt is disabled
1: Interrupt is enabled
8
fault
R/W
0
Multi-Master Fault Interrupt Enable
0: Interrupt is disabled
1: Interrupt is enabled
7:6
-
R/W
0
Reserved for Future Use
Do not modify this field.
5
ssd
R/W
0
Slave Select Deasserted Interrupt Enable
0: Interrupt is disabled
1: Interrupt is enabled
4
ssa
R/W
0
Slave Select Asserted Interrupt Enable
0: Interrupt is disabled
1: Interrupt is enabled
3
rx_full
R/W
0
RX FIFO Full Interrupt Enable
0: Interrupt is disabled
1: Interrupt is enabled
2
rx_level
R/W
RX FIFO Threshold Level Crossed Interrupt Enable
0: Interrupt is disabled
1: Interrupt is enabled
1
tx_empty
R/W
0
TX FIFO Empty Interrupt Enable
0: Interrupt is disabled
1: Interrupt is enabled
0
tx_level
R/W
0
TX FIFO Threshold Level Crossed Interrupt Enable
0: Interrupt is disabled
1: Interrupt is enabled