Maxim Integrated MAX32660 - Table 13-15: SPI Wakeup Status Flags Registers; Table 13-16: SPI Wakeup Enable Registers; Table 13-17: SPI Status Registers

MAX32660 User Guide
Maxim Integrated Page 177 of 195
Table 13-15: SPI Wakeup Status Flags Registers
SPI Wakeup Status Flags
SPI0_WAKE_FL
[0x0028]
Bits
Name
Access
Reset
Description
31:4
-
R/W
0
Reserved for Future Use
Do not modify this field.
3
rx_full
R/W1C
0
Wake on RX FIFO Full Flag
0: Wake condition has not occurred.
1: Wake condition occurred.
2
rx_level
R/W1C
0
Wake on RX FIFO Threshold Level Crossed Flag
0: Wake condition has not occurred.
1: Wake condition occurred.
1
tx_empty
R/W1C
0
Wake on TX FIFO Empty Flag
0: Wake condition has not occurred.
1: Wake condition occurred.
0
tx_level
R/W1C
0
Wake on TX FIFO Threshold Level Crossed Flag
0: Wake condition has not occurred.
1: Wake condition occurred.
Table 13-16: SPI Wakeup Enable Registers
SPI Wakeup Enable
SPI0_WAKE_EN
[0x002C]
Bits
Name
Access
Reset
Description
31:4
-
R/W
0
Reserved for Future Use
Do not modify this field.
3
rx_full
R/W
0
Wake on RX FIFO Full Enable
0: Wake event is disabled
1: Wake event is enabled.
2
rx_level
R/W
0
Wake on RX FIFO Threshold Level Crossed Enable
0: Wake event is disabled
1: Wake event is enabled.
1
tx_empty
R/W
0
Wake on TX FIFO Empty Enable
0: Wake event is disabled
1: Wake event is enabled.
0
tx_level
R/W
0
Wake on TX FIFO Threshold Level Crossed Enable
0: Wake event is disabled
1: Wake event is enabled.
Table 13-17: SPI Status Registers
SPI Status Register
SPI0_STAT
[0x0030]
Bits
Name
Access
Reset
Description
31:1
-
R/W
0
Reserved for Future Use
Do not modify this field.
0
busy
R
0
SPI Active Status
0: SPI is not active. In Master Mode, cleared when the last character is sent. In Slave
Mode, cleared when SS is deasserted.
1: SPI is active. In Master Mode, set when transmit starts. In Slave Mode, set when SS
is asserted.