Maxim Integrated MAX32660 - Table 12-12: I C Receive Control 1 Registers; Table 12-13: I 2 C Transmit Control Registers 0

MAX32660 User Guide
Maxim Integrated Page 153 of 195
Table 12-12: I
2
C Receive Control 1 Registers
I
2
C Receive Control 1 Register
I2Cn_RXCTRL1
[0x0020]
Bits
Name
Access
Reset
Description
31:12
-
R/W
0
Reserved for Future Use
Do not modify this field.
11:8
rxfifo
R
0
RX FIFO Byte Count
Returns the number of bytes currently in the RX FIFO.
0: No data in the RX FIFO.
...
8: 8 bytes in the RX FIFO (max value).
7:0
rxcnt
R/W
1
RX FIFO Transaction Byte Count
When in Master Mode, write the number of bytes to be received in a transaction
from 1 to 256. 0 represents 256.
0: 256 byte receive transaction.
1: 1 byte receive transaction.
2: 2 byte receive transaction.

255: 255 byte receive transaction.
Table 12-13: I
2
C Transmit Control Registers 0
I
2
C Transmit Control Register 0
I2Cn_TXCTRL0
[0x0024]
Bits
Name
Access
Reset
Description
31:12
-
R/W
-
Reserved for Future Use
Do not modify this field.
11:8
txth
R/W
0
TX FIFO Threshold Level
Sets the level for a Transmit FIFO threshold event interrupt. If the number of bytes
remaining in the TX FIFO falls to this level or lower the interrupt flag
I2Cn_INTFL0.txthi is set indicating a TX FIFO Threshold Event occurred.
0: 0 bytes remaining in the TX FIFO triggers a TX FIFO threshold event.
1: 1 byte or less remaining in the TX FIFO triggers a TX FIFO threshold event
(recommended minimum value).

7: 7 or fewer bytes remaining in the TX FIFO triggers a TX FIFO threshold event
7
txfsh
R/W1O
0
TX FIFO Flush
Write this field to 1 to initiate a TX FIFO flush, clearing all remaining data from the
transmit FIFO.
0: TX FIFO flush is complete or not active.
1: Flush the TX FIFO
Note: Hardware automatically clears this bit to 0 after it is written to 1 when the
flush is completed.
Note: If I2Cn_INTFL0.txloi = 1, then I2Cn_TXCTRL0.txfsh = 1.
6:1
-
R/W
0
Reserved for Future Use
Do not modify this field.