Maxim Integrated MAX32660 - Table 10-4: Timer PWM Registers; Table 10-5: Timer Interrupt Registers; Table 10-6: Timer Control Registers

MAX32660 User Guide
Maxim Integrated Page 123 of 195
Table 10-4: Timer PWM Registers
Timer PWM Register
TMRn_PWM
[0x0008]
Bits
Name
Access
Reset
Description
31:0
pwm
R/W
0
Timer PWM Match or Timer Capture Value
PWM Mode:
In PWM mode, this field sets the count value for the first transition period of the PWM
cycle. At the end of the cycle where TMRn_CNT equals TMRn_CMP, the PWM output
transitions to the second period of the PWM cycle. The second PWM period count is
stored in the TMRn_CMP register. The value set for TMRn_PWM.pwm must be less
than the value set in TMRn_CMP for PWM mode operation.
Capture or Capture/Compare Mode:
In Capture, Compare, and Capture/Compare modes, this field is used to store the
TMRn_CNT value when a Capture, Compare, or Capture/Compare event occurs.
Table 10-5: Timer Interrupt Registers
Timer Interrupt Register
TMRn_INT
[0x000C]
Bits
Name
Access
Reset
Description
31:1
-
R
0
Reserved for Future Use
Do not modify this field.
0
irq
RW
0
Timer Interrupt
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Table 10-6: Timer Control Registers
Timer Control Register
TMRn_CN
[0x0010]
Bits
Name
Access
Reset
Description
-
R
0
Reserved for Future Use
Do not modify this field.
12
pwmckbd
R/W
1
PWM Output 

󰆓
Disable
1: Disable PWM Output 

󰆓
0: Enable PWM Output 

󰆓
11
nollpol
R/W
0
PWM Output 

󰆓
Polarity Bit
1: Output 

󰆓
inverted
0: Output 

󰆓
non-inverted
10
nolhpol
R/W
0
PWM Output 

Polarity Bit
1: Output 

inverted
0: Output 

non-inverted
9
pwmsync
R/W
0
PWM Synchronization Mode
1: PWM synchronization mode enabled
0: PWM synchronization mode disabled
8
pres3
R/W
0
Timer Prescale Select MSB
See TMRn_CN.pres for details about this bit.
7
ten
R/W
0
Timer Enable
1: Timer enabled
0: Timer disabled