Maxim Integrated MAX32660 - Table 12-1: I 2 C Bus Terminology

MAX32660 User Guide
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12 I
2
C Master/Slave Serial Controller
The MAX32660 integrates two I
2
C peripherals, designated I2C0 and I2C1. The register interfaces for I2C0 and I2C1 are
identical with the same offset addresses for each register. For simplicity, I2Cn is used throughout this section to refer to
both I
2
C ports (where n = [0,1]). The I2Cn peripheral supports High-speed mode (Hs-mode), Fast-mode and Standard mode
communication speeds. Each I2Cn peripheral can operate as a master or a slave device.
The I
2
C bus is a standardized two-wire, bidirectional serial bus. It uses only two bus lines, a Serial Data Access (SDA) line for
data, and a Serial Clock line (SCL) for the clock. SDA and SCL idle high with external pullup resistors. They are pulled low by
open-drain drivers in the peripherals. Internal pullup circuits in the GPIO pins are capable of holding the SDA line and SCL
line at a logic high state when all devices are idle, but external pullup resistors are highly recommended for all but the
simplest, lowest-capacitance systems.
An I
2
C master owns the I
2
C bus for the duration of a transfer, driving the clock (SCL) and generating START and STOP signals.
In slave mode, the I
2
C Controller relies on an external master to generate the clock on SCL. An I
2
C slave responds to data
and commands only when an I
2
C master device addresses it.
For detailed information on I
2
C bus operation refer to Maxim Application Note 4024: SPI/I²C Bus Lines Control Multiple
Peripherals.
12.1.1 Related Documentation
For details of the I
2
C-bus, please refer to the I
2
C-bus specification and user manual, Rev. 6 - 4 April 2014.
12.1.2 I
2
C Bus Terminology
Table 12-1, below, contains terms and definitions used in this chapter for the I
2
C Bus Terminology.
Table 12-1: I
2
C Bus Terminology
Term
Definition
Transmitter
The device that sends data to the bus.
Receiver
The device that receives data from the bus.
Master
The device that initiates a transfer, generates clock signals and terminates a transfer.
Slave
The device addressed by a master.
Multi-master
More than one master can attempt to control the bus at the same time without corrupting the
message.
Arbitration
Procedure to ensure that, if more than one master simultaneously tries to control the bus, only one
can do so and the resulting message is not corrupted.
Synchronization
Procedure to synchronize the clock signals of two or more devices.
Clock Stretching
When a slave device holds SCL low to pause a transfer until it is ready. This feature is optional
according to the I
2
C Specification; thus, a master does not have to support slave clock stretching if
none of the slaves in the system are capable of clock stretching.
A device attached to the I
2
C-bus assumes one of the following roles and can change between each transaction.
• Master-Transmitter
• Master-Receiver
• Slave-Transmitter
• Slave-Receiver