Maxim Integrated MAX32660 - Table 14-1: Four-Wire SPI Signals; Figure 14-1. SPIMSS Block Diagram

MAX32660 User Guide
Maxim Integrated Page 179 of 195
Figure 14-1. SPIMSS Block Diagram
An SPI system has a single master and one or more slaves for any given transaction. The SPIMSS supports single master
mode networks only when operating in SPI master mode.
14.1.2 Four-Wire SPI Signals
SPI devices operate as either a master or slave device. In four-wire SPI, four signals are required for communication as
shown in Table 14-3, below.
Table 14-1: Four-Wire SPI Signals
Signal
MAX32660
Alternate Function Name
Description
Direction
SCK
SPI1_SCK
Serial Clock
The master generates the Serial Clock signal, which is an output
from the master and an input to the slave.
MOSI
SPI1_MOSI
Master Output Slave Input
In master mode, this signal is used as an output for sending
data to the slave. In slave mode this is the input data from the
master.
MISO
SPI1_MISO
Master Input Slave Output
In master mode, this signal is used as an input for receiving
data from the slave.
In slave mode, this signal is an output for transmitting data to
the master.
SS
SPI1_SS0
Slave Select
In master mode, this signal is an output used to select a slave
device prior to communication.
In slave mode, this signal is an input used to indicate the
master is going to start communication.