Maxim Integrated MAX32660 - Table 8-6: UART Interrupt Enable Register

MAX32660 User Guide
Maxim Integrated Page 91 of 195
UART Status Register
UARTn_STAT
[0x0008]
Bits
Name
Access
Reset
Description
0
tx_busy
RO
0
TX Busy
This field reads 1 when the UART is transmitting data.
0: UART is not actively transmitting data.
1: UART is transmitting data.
Table 8-6: UART Interrupt Enable Register
UART Interrupt Enable Register
UARTn_INT_EN
[0x000C]
Bits
Name
Access
Reset
Description
31:10
-
R/W
0
Reserved for Future Use
Do not modify this field.
9
last_break
R/W
0
Last Break Interrupt Enable
When the UART receives a series of BREAK frames, this enables an interrupt when
the last BREAK frame is received.
0: Interrupt disabled.
1: Interrupt enabled.
8
rx_to
R/W
0
RX Timeout Interrupt Enable
Enable the receive timeout interrupt.
0: Interrupt disabled.
1: Interrupt enabled.
7
break
R/W
0
Received BREAK Interrupt Enable
Enables the BREAK interrupt for the first BREAK received on the UART.
0: Interrupt disabled.
1: Interrupt enabled.
6
tx_fifo_lvl
R/W
0
TX FIFO Threshold Level Interrupt Enable
Set this field to 1 to enable an interrupt when the number of entries in the transmit
FIFO is less than or equal to the UARTn_CTRL1.tx_fifo_lvl field.
0: Interrupt disabled.
1: Interrupt enabled.
5
tx_fifo_ae
R/W
0
TX FIFO Almost Empty Interrupt Enable
Enables an interrupt indicating the transmit FIFO is almost empty, one byte
remaining.
0: Interrupt disabled.
1: Interrupt enabled.
4
rx_fifo_lvl
R/W
0
RX FIFO Threshold Level Interrupt Enable
Set this field to 1 to enable an interrupt when the number of entries in the receive
FIFO is greater than or equal to the UARTn_CTRL1.rx_fifo_lvl field.
0: Interrupt disabled.
1: Interrupt enabled.
3
rx_overrun
R/W
0
RX FIFO Overrun Interrupt Enable
Enables an interrupt when a write is made to a full RX FIFO
0: Interrupt disabled.
1: Interrupt enabled.
2
cts
R/W
0
CTS State Change Interrupt Enable
Enable the CTS level change interrupt event.
0: Interrupt disabled.
1: Interrupt enabled.