MAX32660 User Guide
Maxim Integrated Page 182 of 195
During an SPI transfer, data is sent and received simultaneously by both the master and slave device. When an SPI transfer
occurs, a multi-bit character, selectable from 1-bit to 16 bits, is shifted out on the data output line and a multi-bit character
is simultaneously shifted in on the data input pin. A 16-bit shift register in the master and another 16-bit shift register in the
slave are connected as a circular buffer with the most significant bit (bit15) sent first. The SPIMSS contains two 8 entry, 16-
bit FIFOs to support transmit and receive data. Any data in the transmit FIFO is moved into the shift register at the start of
every new SPI transfer if there is data in the transmit FIFO. At the end of each SPI character transmitted, data is moved from
the input shift register into the receive FIFO.
14.3.1 Serial Clock
The Serial Clock (SCK) synchronizes data movement in and out of the device through the SPI1_MOSI and SPI1_MISO pins.
The master drives the serial clock out its SCK SCK pin. When SPI1 is set to master mode, the SPIMSS bit
rate generator creates the serial clock and outputs it on the SPI1_SCK pin. When SPI1 is configured for slave operation the
SPI1_SCK pin is an input from the external master. Slave devices ignore the SCK signal unless their slave select pin is
asserted.
When SPI1 is configured for slave operation, the maximum SCK input frequency supported is
. For example,
if
, the maximum SPI clock frequency supported in slave mode for SPI1 is 6MHz.
In both master and slave devices, data is shifted on one edge of the SCK and is sampled on the opposite edge where data is
stable. Data availability and sampling time is controlled using the SPI phase control field, SPIMSS_CTRL.phase. The SCK clock
polarity field, SPIMSS_CTRL.clkpol, controls if the SCK signal is active high or active low.
SPIMSS supports four combinations of SCK phase and polarity. Clock Polarity (SPIMSS_CTRL.clkpol) selects an active
low/high clock and has no effect on the transfer format. Clock Phase (SPIMSS_CTRL.phase) selects one of two different
transfer formats.
For proper data transmission, the clock phase and polarity must be identical for the SPI master and slave. The master
always places data on the MOSI line a half-cycle before the SCLK edge for the slave to latch the data.
Table 14-4. Clock Phase and Polarity Operation
14.3.2 SPI Slave Select Configuration
The Slave Select (SS) signal is used to select a specific slave device during SPI transfers or to distinguish left and right
channel audio data in I
2
S mode. In an SPI system with multiple slaves, the master must provide separate slave select signals
to each slave. The slave select is set to active prior to any communication with a slave and must remain in the active state
for the full duration of each character transferred at a minimum. The slave select signal may stay low during the transfer of
multiple characters or may deassert between each character. The SPIMSS_MODE.ssv bit is not used in SPI slave mode.
14.3.2.1 SPI Master Mode
If using SPI1 as a SPI master, set the slave select pin, SPI1_SS0, as an output (SPIMSS_CTRL.ss_io = 1). The polarity of the
slave select signal is selected via the SPIMSS_MODE.ssv bit and defaults to active low (SPIMSS_MODE.ssv).
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