Maxim Integrated MAX32660 - Table 8-7: UART Interrupt Flags Register

MAX32660 User Guide
Maxim Integrated Page 92 of 195
UART Interrupt Enable Register
UARTn_INT_EN
[0x000C]
Bits
Name
Access
Reset
Description
1
rx_parity_error
R/W
0
RX Parity Error Interrupt Enable
Enables an interrupt when a receive parity error is detected.
0: Interrupt disabled.
1: Interrupt enabled.
0
rx_frame_error
R/W
0
RX Frame Error Interrupt Enable
Enables an interrupt when a receive frame error is detected.
0: Interrupt disabled.
1: Interrupt enabled.
Table 8-7: UART Interrupt Flags Register
UART Interrupt Flags Register
UARTn_INT_FL
[0x0010]
Bits
Name
Access
Reset
Description
31:10
-
RO
0
Reserved for Future Use
Do not modify this field.
9
last_break
R/W1C
0
Last Break Interrupt Flag
When the UART receives a series of BREAK frames, this flag is set when the last
BREAK frame is received. Write 1 to clear this field.
0: Last BREAK condition has not occurred.
1: Last BREAK condition has occurred.
8
rx_to
R/W1C
0
Receive Frame Timeout Interrupt Flag
This field is set when a receive frame timeout occurs. Write 1 to clear this field.
0: Receive frame timeout has not occurred.
1: A receive frame timeout was detected by the UART.
7
break
R/W1C
0
Received Break Interrupt Flag
When the UART receives a series of BREAK frames, this flag is set when the first
BREAK frame is received. Write 1 to clear this field.
6
tx_fifo_lvl
R/W1C
0
Transmit FIFO Threshold Interrupt Flag
This interrupt flag is set when number of entries in in the Transmit FIFO is less than
or equal to the Transmit FIFO level set in UARTn_CTRL1.tx_fifo_lvl. Write 1 to clear.
0: TX FIFO level is greater than the UARTn_CTRL1.tx_fifo_lvl.
1: TX FIFO level is equal to or less than the UARTn_CTRL1.tx_fifo_lvl.
Note: This flag is set immediately by hardware when the condition exists. To prevent
additional interrupts from occurring after clearing this flag, write data to the TX FIFO
or decrease the TX FIFO threshold level.
5
tx_fifo_ae
R/W1C
0
Transmit FIFO Almost Empty Interrupt Flag
This field is set when there is one byte remaining in the Transmit FIFO. Write 1 to
clear.
4
rx_fifo_lvl
R/W1C
0
RX FIFO Threshold Interrupt Flag
Set when number of entries in the RX FIFO is equal to or greater than the RX FIFO
threshold level as set in the UARTn_CTRL1.rx_fifo_lvl field. Data must be read from
the RX FIFO to reduce the level below the threshold to guarantee this interrupt does
not occur again after clearing the flag. Write 1 to clear this field.
0: The number of bytes in the RX FIFO is below the threshold level.
1: The number of bytes in the RX FIFO is equal to or greater than the threshold
level.