Maxim Integrated MAX32660 - Table 4-12: Global Control Registers, Offsets and Descriptions; Table 4-13: System Control Register

MAX32660 User Guide
Maxim Integrated Page 33 of 195
4.10.3 RAM Low Power Modes
RAM can be placed in a low power mode, referred to as Light Sleep, using register GCR_MEM_CTRL, Memory Clock Control.
Light Sleep gates off the clock to the RAM and makes the RAM unavailable for read/write operations. The RAM contents are
retained during Light Sleep mode. Light Sleep is available for the internal Data RAM blocks as well as for the ICC0 cache
RAM. Turning off Light Sleep mode for a memory enables Read/Write to that memory range.
RAM can also be shut down for power savings using the register PWRSEQ_LPMEMSD, RAM Shut Down Control. This
conserves power by gating off the power and clock to the RAM. This invalidates the contents of the RAM and the RAM is
not accessible until the RAM shutdown mode is disabled. When enabling a RAM partition from a shutdown state, the RAM
contents are cleared.
4.11 Global Control Registers (GCR)
The GCR base peripheral address is 0x4000 0000. Refer to Table 3-1: APB Peripheral Base Address Map for the addresses of
all APB mapped peripherals.
The Global Control Registers are only reset on a System Reset, Watchdog Timer Reset and a Power-On Reset. Soft Reset and
Peripheral Reset do not affect these registers.
Table 4-12: Global Control Registers, Offsets and Descriptions
Offset
Register Name
Access
Description
[0x0000]
GCR_SCON
R/W
System Control Register
[0x0004]
GCR_RST0
R/W
Reset Register 0
[0x0008]
GCR_CLK_CTRL
R/W
Clock Control Register
[0x000C]
GCR_PM
R/W
Power Management Register
[0x0024]
GCR_PCLK_DIS0
R/W
Peripheral Clocks Disable 0
[0x0028]
GCR_MEM_CTRL
R/W
Memory Clock Control
[0x002C]
GCR_MEM_ZCTRL
R/W
Memory Zeroize Register
[0x0040]
GCR_SYS_STAT
RO
System Status Flags
[0x0044]
GCR_RST1
R/W
Reset Register 1
[0x0048]
GCR_PCLK_DIS1
R/W
Peripheral Clocks Disable 1
[0x004C]
GCR_EVTEN
R/W
Event Enable Register
[0x0050]
GCR_REV
RO
Revision Register
[0x0054]
GCR_SYS_IE
R/W
System Status Interrupt Enable
4.11.1 Global Control Register Details
Table 4-13: System Control Register
System Control Register
GCR_SCON
[0x0000]
Bits
Name
Access
Reset
Description
31:15
-
RO
-
Reserved for Future Use
Do not modify this field.