Maxim Integrated MAX32660 - Table 12-3: I C Registers

MAX32660 User Guide
Maxim Integrated Page 144 of 195
The required steps for implementing TX FIFO Preloading in an application are as follow:
1. Set I2Cn_TXCTRL1.txrdy to 0
2. Enable TX FIFO Preloading by setting I2Cn_TXCTRL1.txpreld to 1.
3. If the TX FIFO Lockout Flag (I2Cn_INTFL0.txloi) is set to 1, write 1 to clear the flag and enable writes to the TX FIFO.
4. Enable DMA or Interrupts if required.
5. Load the TX FIFO with the data to send when the Master sends the next read request.
6. Set I2Cn_TXCTRL1.txrdy to 1 to automatically let the hardware send the preloaded FIFO on the next read from a
Master.
7. I2Cn_TXCTRL1.txrdy is cleared by hardware when a read occurs, and data is transmitted from the TX FIFO.
a. Once cleared, the application firmware may repeat the Preloading process or disable TX FIFO Preloading.
Note: The TX FIFO Lockout flag is set if an error condition occurs while TX FIFO Preloading is enabled.
12.15 Master Mode Receiver Operation
When in Master Mode, initiating a Master Receiver operation begins with the following sequence:
1. Write the number of data bytes to receive to the I
2
C Receive Count field (I2Cn_RXCTRL1.rxcnt).
2. Write the Slave Address to the TX FIFO with the R/W bit set to 1
3. Send a START condition by setting I2Cn_MSTR_MODE.start = 1
4. The slave address is transmitted by the controller from the TX FIFO.
5. The I
2
C controller receives an ACK from the slave and the controller sets address ACK field
(I2Cn_INTFL0.adracki = 1).
6. The I
2
C controller receives data from the slave and automatically ACKs each byte.
7. Once I2Cn_RXCTRL1.rxcnt data bytes have been received, the I
2
C controller sends a NACK to the slave and sets the
Transfer Done Interrupt Status Flag (I2Cn_INTFL0.donei = 1).
8. If I2Cn_MSTR_MODE.restart or I2Cn_MSTR_MODE.stop is set, then the I
2
C controller sends a repeated START or
STOP, respectively.
12.16 I
2
C Registers
The I2C0 base peripheral address is 0x4001 D000. The I2C1 base peripheral address is 0x4001 E000. Refer to Table 3-1: APB
Peripheral Base Address Map for the addresses of all APB mapped peripherals.
Table 12-3: I
2
C Registers
Offset
Register Name
Access
Description
[0x0000]
I2Cn_CTRL0
R/W
I
2
C Control 0 Register
[0x0004]
I2Cn_STATUS
RO
I
2
C Status Register
[0x0008]
I2Cn_INTFL0
R/W1C
I
2
C Interrupt Flags 0 Register
[0x000C]
I2Cn_INTEN0
R/W
I
2
C Interrupt Enable 0 Register
[0x0010]
I2Cn_INTFL1
R/W1C
I
2
C Interrupts Flags 1 Register
[0x0014]
I2Cn_INTEN1
R/W
I
2
C Interrupts Enable 1 Register
[0x0018]
I2Cn_FIFOLEN
RO
I
2
C FIFO Length Register
[0x001C]
I2Cn_RXCTRL0
R/W
I
2
C Receive Control 0 Register
[0x0020]
I2Cn_RXCTRL1
R/W
I
2
C Receive Control 1 Register 1
[0x0024]
I2Cn_TXCTRL0
R/W
I
2
C Transmit Control 0 Register 0
[0x0028]
I2Cn_TXCTRL1
R/W
I
2
C Transmit Control 1 Register 1
[0x002C]
I2Cn_FIFO
R/W
I
2
C Transmit and Receive FIFO Register
[0x0030]
I2Cn_MSTR_MODE
R/W
I
2
C Master Mode Register