Maxim Integrated MAX32660 - Table 13-13: SPI Interrupt Flag Registers

MAX32660 User Guide
Maxim Integrated Page 174 of 195
SPI DMA Control Register
SPI0_DMA
[0x001C]
Bits
Name
Access
Reset
Description
20:16
rx_fifo_level
R/W
0
RX FIFO Threshold Level
When the RX FIFO contains more bytes than the value set in this field, a DMA request
is triggered, and the SPI0_INT_FL.rx_level interrupt flag is set. Valid levels for this field
are from 0x00 to 0x1E.
0x00: 1 byte in the RX FIFO generates a SPI0_INT_FL.rx_level interrupt flag.
0x01: 2 bytes in the RX FIFO generates an interrupt.

n: n+1 bytes in the RX FIFO sets the SPI0_INT_FL.rx_level interrupt flag.

0x1E: Maximum allowed value for this field. 0x1F bytes in the RX FIFO set the
SPI0_INT_FL.rx_level interrupt flag.
0x1F is not a valid value.
15
tx_dma_en
R/W
0
TX DMA Enable
0: TX DMA is disabled. Any pending DMA requests are cleared
1: TX DMA is enabled
14
-
R/W
0
Reserved for Future Use
Do not modify this field.
13:8
tx_fifo_cnt
R0
0
Number of Bytes in the TX FIFO
Read returns the number of bytes currently in the TX FIFO
7
tx_fifo_clear
W1O
-
Clear the TX FIFO
Set this field to flush the TX FIFO. Write 1 only. Write 0 is ignored.
0: TX FIFO flush not active.
1: Clear the TX FIFO and any pending TX FIFO flags in SPI0_INT_FL. This should be
done when the TX FIFO is inactive.
Note: Writing 0 has no effect.
6
tx_fifo_en
R/W
0
TX FIFO Enabled
Enable the TX FIFO by setting this field to 1.
0: TX FIFO disabled
1: TX FIFO enabled
5
-
R/W
0
Reserved for Future Use
Do not modify this field.
4:0
tx_fifo_level
R/W
0x10
TX FIFO Threshold Level
When the TX FIFO has fewer than the value set in this field, a DMA request is
triggered, and the SPI0_INT_FL.tx_level interrupt flag is set.
Table 13-13: SPI Interrupt Flag Registers
SPI Interrupt Flag Register
SPI0_INT_FL
[0x0020]
Bits
Name
Access
Reset
Description
31:16
-
R/W1C
0
Reserved for Future Use
Do not modify this field.
15
rx_und
R/W1C
0
RX FIFO Underrun Flag
Set when a read is attempted from an empty RX FIFO.
14
rx_ovr
R/W1C
0
RX FIFO Overrun Flag
Set if SPI is in Slave Mode, and a write to a full RX FIFO is attempted. If the SPI is in
Master Mode, this bit is not set as the SPI stalls the clock until data is read from the RX
FIFO.