Maxim Integrated MAX32660 - Table 7-9: Standard DMA Channel 0 to Channel 15 Offsets; Table 7-10: Dman Channel Registers, Offsets, Access and Descriptions

MAX32660 User Guide
Maxim Integrated Page 78 of 195
DMA Interrupt Flag Register
DMA_INT_FL
[0x0004]
Bits
Name
Access
Reset
Description
30
ipend
RO
0
Channel Interrupt
Each bit in this field represents an interrupt for the corresponding channel. To clear an
interrupt, clear the corresponding active interrupt bit in the DMAn_STAT register. An
interrupt bit in this field is set only if the corresponding channel interrupt enable field
is set in the DMAn_CFG register.
0: No interrupt
1: Interrupt pending
7.14 Standard DMA Channel 0 to 3 Register Base Addresses
Each DMA channel has a set of associated Configuration Registers as shown in Table 7-10. 
configuration registers requires adding the channel base address from Table 7-9 and the offset of the desired configuration
register from Table 7-10. For example, 
Address, 0x4002 0160, plus the offset of the DMAn_DST_RLD register, [0x0018] which gives the address 0x4002 0178 for
DMA3_DST_RLD.
Table 7-9: Standard DMA Channel 0 to Channel 15 Offsets
Channel
Base Address
DMA
Channel
Access
Description
0x4002 8100
0
R/W
DMA Channel 0
0x4002 0120
1
R/W
DMA Channel 1
0x4002 0140
2
R/W
DMA Channel 2
0x4002 0160
3
R/W
DMA Channel 3
7.15 Standard DMA Channel Configuration Register Offsets
Table 7-10: DMAn Channel Registers, Offsets, Access and Descriptions
Address
Register
Access
Description
[0x0000]
DMAn_CFG
R/W
DMA Channel Configuration Register
[0x0004]
DMAn_STAT
R/W
DMA Channel Status Register
[0x0008]
DMAn_SRC
R/W
DMA Channel Source Register
[0x000C]
DMAn_DST
R/W
DMA Channel Destination Register
[0x0010]
DMAn_CNT
R/W
DMA Channel Count Register
[0x0014]
DMAn_SRC_RLD
R/W
DMA Channel Source Reload Register
[0x0018]
DMAn_DST_RLD
R/W
DMA Channel Destination Reload Register
[0x001C]
DMAn_CNT_RLD
R/W
DMA Channel Count Reload Register