Maxim Integrated MAX32660 - Table 5-3: Page Boundary Address Range for Page Erase Operations

MAX32660 User Guide
Maxim Integrated Page 53 of 195
5.3.4 Flash Write
Perform the following steps to write to the internal flash memory:
1. If desired, enable Flash Controller interrupts by setting the FLC_INTR.access_fail_ie and FLC_INTR.done_ie bits.
2. Set the write field, FLC_CTRL.width, as described in Flash Write Width.
3. Set the FLC_ADDR register to a valid target address. Reference Table 5-2.
4. Set the data register or registers.
5. For 32-bit write width, set FLC_DATA0 to the data to write.
6. For 128-bit write width, set FLC_DATA3, FLC_DATA2, FLC_DATA1, and FLC_DATA0 to the data to write. FLC_DATA3
is the most significant word and FLC_DATA0 is the least significant word.
7. Set FLC_CTRL.unlock to 0x2 to unlock the internal flash.
8. Read the FLC_CTRL.busy bit until it returns 0.
9. Start the flash write, set FLC_CTRL.write to 1 and this field is automatically cleared by the Flash Controller when
the write operation is finished.
10. FLC_INTR.done is set by hardware when the write completes and if an error occurred, the FLC_INTR.access_fail flag
is set. These bits generate a flash IRQ if the interrupt enable bits are set.
5.3.5 Page Erase
Perform the following to erase a page of internal flash memory:
1. If desired, enable Flash Controller interrupts by setting the FLC_INTR.access_fail_ie and FLC_INTR.done_ie bits.
2. Set the FLC_ADDR register to a page address to erase. FLC_ADDR[12:0] are ignored by the Flash Controller to
ensure the address is page aligned. Refer to Table 5-3 for the valid page aligned addresses for the internal flash
memory.
3. Set FLC_CTRL.unlock to 0x2 to unlock the internal flash.
4. Read the FLC_CTRL.busy bit until it returns 0.
5. Set FLC_CTRL.erase_code to 0x55 for page erase.
6. Set FLC_CTRL.page_erase to 1 to start the page erase operation.
7. The FLC_CTRL.busy bit is set by the Flash Controller while the page erase is in progress and the
FLC_CTRL.page_erase and FLC_CTRL.busy are cleared by the Flash Controller when the page erase is complete.
8. FLC_INTR.done is set by hardware when the page erase completes and if an error occurred, the
FLC_INTR.access_fail flag is set. These bits generate a flash IRQ if the interrupt enable bits are set.
Table 5-3: Page Boundary Address Range for Page Erase Operations
FLC_ADDR[31:0]
Bit Number
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Page Aligned
Address
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x
x
x
x
x
0
0
0
0
0
0
0
0
0
0
0
0
0