MAX32660 User Guide
Maxim Integrated Page 90 of 195
Table 8-5: UART Status Register
Reserved for Future Use
Do not modify this field.
RX Timeout
This field is set to 1 when a receive timeout occurs. This field is set by hardware when
the condition occurs and is automatically cleared when the condition is no longer
valid.
Reserved for Future Use
Do not modify this field.
Number of Bytes in the TX FIFO
Read this field to determine the number of bytes in the transmit FIFO.
Reserved for Future Use
Do not modify this field.
Number of Byes in RX FIFO
Read this field to determine the number of bytes in the receive FIFO.
TX FIFO Full Status Flag
This field reads 1 when the TX FIFO is full. This field is set by hardware when the
condition occurs and is automatically cleared when the condition is no longer valid.
0: TX FIFO is not full.
1: TX FIFO is full.
TX FIFO Empty Flag
This field reads 1 when the TX FIFO is empty. This field is set by hardware when the
condition occurs and is automatically cleared when the condition is no longer valid.
0: TX FIFO is not empty, UARTn_STAT.tx_num > 0.
1: TX FIFO is empty.
RX FIFO Full Flag
This field reads 1 when then RX FIFO is full. This field is set by hardware when the
condition occurs and is automatically cleared when the condition is no longer valid.
0: RX FIFO is not full.
1: RX FIFO is full.
RX FIFO Empty Flag
This flag reads 1 when the RX FIFO is empty.
Break Flag
This field is set when a break condition occurs.
0: BREAK not received.
1: BREAK condition received.
Parity Bit State
This field returns the state of the parity bit.
0: Parity bit is 0.
1: Parity bit is 1.
RX Busy
This field reads 1 when the UART is receiving data.
0: UART is not actively receiving data.
1: UART is actively receiving data.