Maxim Integrated MAX32660 - Table 4-33: Low Power Mode Wakeup Flags for GPIO0; Table 4-34: Low Power Wakeup Enable for GPIO0 Register; Table 4-35: RAM Shut down Register

MAX32660 User Guide
Maxim Integrated Page 49 of 195
Low Power Voltage Control Register
PWRSEQ_LP_CTRL
[0x0000]
Bits
Name
Access
Reset
Description
0
ramret_sel0
R/W
0
System RAM 0 Data Retention Enable for BACKUP Mode
Set this field to 1 to enable Data Retention for System RAM 0, address range of
0x2000 0000 to 0x2000 3FFF.
0: Data retention for System RAM 0 address space disabled in BACKUP mode.
1: Data retention for System RAM 0 address space enabled in BACKUP mode.
Table 4-33: Low Power Mode Wakeup Flags for GPIO0
Low Power Mode GPIO Wakeup Flags Register
PWRSEQ_LP_WAKEFL
[0x0004]
Bits
Name
Access
Reset
Description
31:14
-
R/W1C
0
Reserved for Future Use
Do not modify this field.
13:0
wakest
R/W1C
0
GPIO Pin Wakeup Status Flag
When a GPIO pin transitions from low-to-high or high-to-low, the corresponding bit in
this field is set.
If the corresponding interrupt enable bit is set in PWRSEQ_LPWK_EN register and
GCR_PM.gpiowk_en bit is set to 1, a PWRSEQ IRQ is generated to wake up the device
from all low power modes to ACTIVE mode.
Note: To enable the device to wake up from a low power mode on a GPIO pin
transition, first set the GCR_PM GPIO wakeup enable field to 1
(GCR_PM.gpiowk_en = 1).
Table 4-34: Low Power Wakeup Enable for GPIO0 Register
Low Power Mode Wakeup Enable for GPIO0
PWRSEQ_LPWK_EN
[0x0008]
Bits
Name
Access
Reset
Description
31:14
-
R/W
0
Reserved for Future Use
Do not modify this field.
13:0
wakeen
R/W
0
GPIO Pin Wakeup Interrupt Enable
Write 1 to a bit to enable the corresponding GPIO0 pin to generate a PWRSEQ IRQ to
wake up the device from any low power mode to ACTIVE mode. Set the
GCR_PM.gpiowk_en bit to 1 to enable GPIO wake up events.
A wake up occurs on any low-to-high or high-to-low transition on the corresponding
GPIO0 pin.
Note: To enable the device to wake up from a low power mode on a GPIO pin transition,
first set the global GPIO wakeup enable field, (GCR_PM.gpiowk_en = 1).
Table 4-35: RAM Shut Down Register
Low-Power Memory Shutdown Register
PWRSEQ_LPMEMSD
[0x0040]
Bits
Name
Access
Reset
Description
31:4
-
RO
-
Reserved for Future Use
Do not modify this field.
3
sram3_off
R/W
0
System RAM 3 (0x2001 0000 - 0x2001 7FFF) Shut Down
Write 1 to shut down power to System RAM 3 memory range.
0: System RAM 3 Powered On (Enabled)
1: System RAM 3 Powered Off (Disabled)