Maxim Integrated MAX32660 - Table 6-12: GPIO Input Register; Table 6-13: GPIO Port Interrupt Mode Register; Table 6-14: GPIO Port Interrupt Polarity Registers; Table 6-15: GPIO Port Interrupt Enable Registers

MAX32660 User Guide
Maxim Integrated Page 65 of 195
Table 6-12: GPIO Input Register
GPIO Input Register
GPIO0_IN
[0x0024]
Bits
Name
Access
Reset
Description
31:14
-
R/W
0
Reserved for Future Use
Do not modify this field.
13:0
-
RO
-
GPIO Input Level
Read the state of the corresponding input pin. The input state is always readable for a
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0: Input pin low (logic 0)
1: Input pin high (logic 1)
Table 6-13: GPIO Port Interrupt Mode Register
GPIO Port Interrupt Mode Register
GPIO0_INT_MODE
[0x0028]
Bits
Name
Access
Reset
Description
31:14
-
R/W
0
Reserved for Future Use
Do not modify this field.
13:0
-
R/W
0
GPIO Interrupt Mode
Interrupt mode selection bit for the corresponding GPIO pin.
0: Level triggered interrupt for corresponding GPIO pin.
1: Edge triggered interrupt for corresponding GPIO pin.
Note: This bit has no effect unless the corresponding bit in the GPIO0_INT_EN register
is set.
Table 6-14: GPIO Port Interrupt Polarity Registers
GPIO Interrupt Polarity Register
GPIO0_INT_POL
[0x002C]
Bits
Name
Access
Reset
Description
31:14
-
R/W
0
Reserved for Future Use
Do not modify this field.
13:0
-
R/W
0
GPIO Interrupt Polarity
Interrupt polarity selection bit for the corresponding GPIO pin.
Level triggered mode (GPIO0_INT_MODE = 0):
0: Input low (logic 0) triggers interrupt.
1: Input high (logic 1) triggers interrupt.
Edge triggered mode (GPIO0_INT_MODE = 1):
0: Falling edge triggers interrupt
1: Rising edge triggers interrupt.
Note: This bit has no effect unless the corresponding bit in the GPIO0_INT_EN register
is set.
Table 6-15: GPIO Port Interrupt Enable Registers
GPIO Interrupt Enable Register
GPIO0_INT_EN
[0x0034]
Bits
Name
Access
Reset
Description
31:14
-
R/W
0
Reserved for Future Use
Do not modify this field.