4.14 Power Supply Monitoring
MAX32660 has a power monitor that monitors the external supply voltages during operation. The following power supplies
are monitored:
• V
CORE
(VCORE) Supply Voltage, CPU Core
• V
DD
(VDD) Supply Voltage
Each of these supplies has a dedicated power monitor setting in the Power Sequencer Low Power Voltage Control Register,
PWRSEQ_LP_CTRL. When the corresponding power monitor is enabled, the input voltage pin is constantly monitored. If the
voltage drops below the trigger threshold, all registers and peripherals in that power domain are reset. This improves
reliability and safety by guarding against a low voltage condition corrupting the contents of the registers and the device
state. Disabling a power monitor risks data corruption of internal registers and corruption of the device state should the
input voltage drop below the safe minimum value.
V
CORE
has a power fail monitor. When enabled, if the power supply drops below the power fail reset voltage the entire
device goes into a Power-On Reset.
Refer to the MAX32660 datasheet for the trigger threshold value and power fail reset voltage. When the power supply
monitor is tripped, a Power Fail Warning Interrupt is triggered.
4.15 Power Sequencer Registers
The PWRSEQ base peripheral address is 0x4000 6800. Refer to Table 3-1: APB Peripheral Base Address Map for the
addresses of all APB mapped peripherals.
Table 4-31: Power Sequencer Low Power Control Registers, Offsets, Access and Descriptions
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