MAX32660 User Guide
Maxim Integrated Page 130 of 195
Watchdog Timer 0 Control Register
Reset Period
Sets the number of PCLK cycles until a system reset occurs if the watchdog timer is
not reset.
0xF:
0xE:
0xD:
0xC:
0xB:
0xA:
0x9:
0x8:
0x7:
0x6:
0x5:
0x4:
0x3:
0x2:
0x1:
0x0:
Interrupt Period
Sets the number of PCLK cycles until a watchdog timer interrupt is generated.
0xF:
0xE:
0xD:
0xC:
0xB:
0xA:
0x9:
0x8:
0x7:
0x6:
0x5:
0x4:
0x3:
0x2:
0x1:
0x0:
Table 11-4: Watchdog Timer Reset Register
Watchdog Timer 0 Reset Register
Reserved for Future Use
Do not modify this field.
Reset Register
Writing the watchdog counter reset sequence to this register resets the
watchdog counter. The following is the required reset sequence to reset the
watchdog and prevent a watchdog timer interrupt or watchdog system reset.
• Write WDT0_RST: 0x0000 00A5
• Write WDT0_RST: 0x0000 005A
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