MAX32660 User Guide
Maxim Integrated Page 183 of 195
14.3.2.2 SPI Slave Mode
When using SPI slave mode, SPIMSS_CTRL.mode = 0, configure the slave select pin, SPI1_SS0, as an input by clearing
SPIMSS_CTRL.ss_io. The SPIMSS_MODE.ssv bit is not used in SPI slave mode.
14.3.3 SPI Character Size
SPI transmits and receives characters simultaneously. The transmit and receive character size is the same. Set the number
of bits per character using the SPIMSS_MODE.numbits field.
14.3.4 SPI Data Movement
Data movement in SPI mode is controlled using one of the following methods:
• Synchronous operation
Application polling of the SPIMSS_INT_FL.txst bit to transfer single words.
Application polling of the SPIMSS_DMA.tx_fifo_level or SPIMSS_DMA.rx_fifo_level fields enables transfers of up
to eight characters at a time.
• Asynchronous Operation
The SPIMSS_CTRL.irqe bit can be set to enable data and error interrupts. The SPIMSS_CTRL.str bit may be used if
transfer.
• DMA Operation
Control of data transferred is enabled via the SPIMSS_DMA.rx_dma_en and/or SPIMSS_DMA.tx_dma_en bits.
The SPIMSS_DMA.tx_fifo_level and SPIMSS_DMA.rx_fifo_level control when DMA requests are asserted. When
DMA is enabled, the SPIMSS data interrupt is disabled by hardware, error interrupts remain available. DMA
operation is beneficial for block transfers as the CPU only needs to service one DMA interrupt per block of data
versus one interrupt for each character transferred if data interrupt-based transfer is used.
The SPIMSS Data Register, SPIMSS_DATA, is used for transferring data for both transmit and receive operations.
For incoming data, the receive data is shifted into an internal shift register. Once a full character is received, the character is
automatically moved into the receive FIFO. Read received data using the SPIMSS_DATA register.
For outgoing data, data written to the SPIMSS_DATA register is automatically moved to the transmit FIFO. The data is then
transmitted via the shift register. When the shift register is empty, any data in the transmit FIFO is moved to the shift
register.
Note: When the SPIMSS is not actively transmitting or receiving data (SPIMSS_CTRL.enable = 0), data written to the SPIMSS
Data Register is stored in the transmit FIFO, if the transmit FIFO is not full. Any data in the transmit FIFO when the SPIMSS
enable bit is set to 1 is transmitted immediately by the hardware. Flush the transmit FIFO at any time by setting the
SPIMSS_DMA.tx_fifo_clr bit to 1.
With the SPIMSS configured as a SPI master, writing data to the SPIMSS_DATA register initiates the data transmission. With
the SPIMSS configured as a SPI slave, writing data SPIMSS_DATA register loads the shift register in preparation for the next
data transfer with the external master. In either SPI master or slave mode, when the transmit FIFO is full, writes to the
SPIMSS_DATA register are ignored and result in a transmit overrun error interrupt (SPIMSS_INT_FL.tovr = 1).
Data is shifted out starting with the most significant bit first (bit 15). The last bit received will reside in the least significant
bit, (bit 0). In SPI mode, when the character length is less than 16 bits, set by the SPIMSS_MODE.numbits field, the transmit
character must be left justified in the SPIMSS_DATA register. A received character of less than 16 bits is always right
justified, with the last bit received loaded into the least significant bit (bit 0). For example, if SPI1 is configured for 4-bit
characters, write transmit data to SPIMSS_DATA[15:12] and received characters are read from SPIMSS_DATA[3:0].
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