MAX32660 User Guide
Maxim Integrated Page 178 of 195
14 SPIMSS (SPI1/I
2
S)
14.1 Overview
The SPIMSS peripheral provides either an SPI interface or an I
2
S interface. When set to SPI mode, the peripheral supports
SPI with a four-wire full-duplex serial bus operating as either a master or slave. When set to I
2
S mode, the peripheral
support full-duplex bi-directional I/O, a signal for Left/Right clock and a bit rate clock signal for master or slave
communications.
The SPIMSS (SPI1/I
2
S) peripheral supports Inter-IC Sound (I
2
S) protocol for 16-bit mono or stereo audio transfer to or from
an external I
2
S audio codec.
14.1.1 Features
• Dedicated Bit Rate Generator
• Eight entry, 16-bit wide transmit and receive FIFOs
• DMA support for both transmit and receive operations
• SPI Features
Full-duplex, synchronous communication of 1 to 16-bit characters
Four-wire interface
Data transfers rates up to one-fourth the peripheral clock frequency (
)
Master and Slave mode SPI operation
1 Slave Select Pin
• I
2
S Features
16-bit audio transfer
I
2
S master or slave mode
Bidirectional, full-duplex communication supported
Left-Right Clock and Bit Clock generation in I
2
S master mode
Figure 14-1 shows a high-level block diagram of the SPIMSS peripheral including the external interface signals, control unit,
receive and transmit FIFOs, and single shift register common to the transmit and receive data path for SPI or I
2
S operation.
The SPIMSS peripheral is configurable to operate as a SPI port or an I
2
S port. The same physical pins are used for SPI or I
2
S
operation. The reset default sets the SPIMSS to SPI operation. Enabling I
2
S, setting SPIMSS_I2S_CTRL.i2s_en to 1, results in
hardware using the pins as defined for I
2
S.
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