MAX32660 User Guide
Maxim Integrated Page 188 of 195
14.6.4 Bit Rate Generator Time-out Interrupt
If the SPI is disabled, an SPI interrupt can be generated by a Bit Rate Generator time-out. This timer function must be
enabled by setting the SPIMSS_CTRL.birq bit to 1.
14.7 SPIMSS Bit Rate Generator
14.7.1 SPI and I
2
S Slave Mode
The Bit Rate Generator is not used in SPI or I
2
S slave mode. When configured as a SPI or I
2
S slave, the maximum SCK or BCLK
frequency is
.
14.7.2 SPI and I
2
S Master Mode Bit Rate Generator
For SPI or I
2
S master operation, the Bit Rate Generator (BRG) creates a lower frequency clock for SCK or BCLK for data
transmission synchronization between the master and the external slave. The input to the Bit Rate Generator is the System
Peripheral clock, PCLK. The Bit Rate Generator register is a 16-bit reload value, SPIMSS_BRG.div, for the Bit Rate Generator.
The reload value, SPIMSS_BRG.div, must be greater than or equal to 0x02 for SPI and I
2
S master operation with a maximum
bit rate frequency of
. Equation 14-1 shows the equation for calculating the SPI master and I
2
S master bit rate
frequency.
Equation 14-1: SPI Master and I
2
S Master Bit Rate Calculation
14.7.3 Timer Mode
When SPI1 or I
2
S is not active, the Bit Rate Generator can function as a continuous mode 16-bit timer with interrupt on
time-out. To configure the Bit Rate Generator as a timer with interrupt on time-out, complete the following procedure:
1. Set SPIMSS_CTRL.enable = 0 to stop any SPI or I
2
S activity.
2. Disable the transmit and receive FIFOs
a. SPIMSS_DMA.tx_fifo_en = 0
b. SPIMSS_DMA.rx_fifo_en = 0
3. Disable DMA mode
a. SPIMSS_DMA.tx_dma_en = 0
b. SPIMSS_DMA.rx_dma_en = 0
4. Load the desired 16-bit divisor into the SPIMSS Bit Rate Generator Register, SPIMSS_BRG.div.
5. Set SPIMSS_CTRL.birq = 1 to enable the Bit Rate Generator
6. Enable the SPIMSS peripheral by setting SPIMSS_CTRL.enable = 1
14.8 SPIMSS (SPI1/I
2
S) Registers
The SPIMSS base peripheral address is 0x4001 9000. Refer to Table 3-1: APB Peripheral Base Address Map for the addresses
of all APB mapped peripherals.
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