Maxim Integrated MAX32660 - Page 187

MAX32660 User Guide
Maxim Integrated Page 187 of 195
14.5.2 SPI Slave Mode Abort
A SPI slave mode abort error indicates that the SPI1_SS0 pin deasserted before all bits in a character were transferred. The
next time SPI1_SS0 asserts, the SPI1_MISO pin outputs SPIMSS_DATA[15], regardless of where the previous transaction
aborted. A slave mode abort sets the SPIMSS_INT_FL.abt error flag to 1. Writing a 1 to SPIMSS_INT_FL.abt clears this error
flag.
Note: This error interrupt does not occur in SPI Master or I
2
S mode.
14.5.3 Receive Overrun
This error occurs if data is received and the Receive FIFO is full and applies to SPI master, SPI slave and I
2
S modes. The
SPIMSS_INT_FL.rovr error flag is set to 1 if this error occurs. Writing a 1 to SPIMSS_INT_FL.rovr bit clears this error flag.
Note: A Receive Overrun error in I
2
S mode results in left/right channel data corruption. If a Receive Overrun error occurs, the
application must flush the Receive FIFO, reinitialize the receive DMA channel, restart the I
2
S transfer.
14.6 SPI1 and I
2
S Interrupts
The SPIMSS provides interrupt support for a variety of conditions for SPI and I
2
S modes. Setting SPIMSS_CTRL.irqe to 1
enables the SPIMSS IRQ. The SPIMSS generates an IRQ when one of the following interrupt conditions occur.
14.6.1 Data Interrupt
A data interrupt occurs when a the Transmit FIFO is empty and the transmit shift register shifts out the last bit of the active
transmit word The Data Interrupt flag applies to both transmit and receive data for SPI and I
2
S because the transmit and
receive paths are interlocked.
The data interrupt does not occur if either Transmit DMA or Receive DMA is enabled because the DMA interface handles
the data interrupt condition directly in hardware.
A data interrupt is indicated as follows:
• The SPIMSS_INT_FL.irq flag is set to 1.
• No error condition flags are set in the SPIMSS_INT_FL register.
 SPIMSS_INT_FL[6:2] = 0
Clear the data interrupt condition by writing 1 to SPIMSS_INT_FL.irq.
14.6.2 Forced Interrupt
To start the data transfer process, an SPI interrupt may be forced by software by writing a 1 to the SPIMSS_CTRL.str bit in
the SPI Control Register.
14.6.3 Error Condition Interrupt
If any of the SPI error conditions occurs as described in section SPI and I2S Error Detection, above, the corresponding error
bit in the SPIMSS_INT_FL register and the SPIMSS_INT_FL.irq bit are set to 1. The error flags and the irq bit should be
cleared simultaneously by writing both to 1 simultaneously. For example, a transmit overrun error is indicated by the
SPIMSS_INT_FL.tovr bit set to 1 and the SPIMSS_INT_FL.irq bit set to 1. Clear this condition by writing 0x06 to
SPIMSS_INT_FL.