MAX32660 User Guide
Maxim Integrated Page 85 of 195
8.3 UART Interrupts
Interrupts can be generated for the following conditions:
• The Transmit FIFO level is equal or less than the set transmit threshold.
• The Receive FIFO level is equal or greater than the set receieve threshold.
• The Receive FIFO is overrun, which means the Receive FIFO is full but is still receiving data
• Any CTS state change. During Hardware Flow Control, this interrupt is generated either because:
CTS is deasserted, which tells the UART to pause transmitting data
CTS is asserted, which tells the UART to resume transmitting data
• A Receive Parity Error occurred
• A Receive Frame Error occurred, which means START or STOP bits were not detected
• A Receive Timeout condition occurred, which means the RX FIFO has not received a character for a set time
• First and Last BREAK characters
8.4 UART Bit Rate Calculation
The UART peripheral clock,
, is used as the input clock to the UART bit rate generator. The following fields are used to
set the target bit rate for the UART.
• UARTn_BAUD0.clk_div selects the bit rate clock divisor.
• UARTn_BAUD0.ibaud sets the integer portion of the bit rate divisor.
• UARTn_BAUD1.dbaud sets the decimal portion of the bit rate divisor.
Equation 8-1, Equation 8-2, and Equation 8-3 are used to determine the values for each of the bit rate fields required to
achieve a target bit rate for the UART.
Equation 8-1: UART Bit Rate Divisor Equation
Note: UARTn_BAUD0.clkdiv should be set to the highest value that results in
to achieve the highest accuracy for
the target bit rate.
Equation 8-2: Bit Rate Integer Calculation
Equation 8-3: Bit Rate Remainder Calculation
8.4.1 Example Baud Rate Calculation:
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