Maxim Integrated MAX32660 - Page 128

MAX32660 User Guide
Maxim Integrated Page 128 of 195
WDT0_CTRL
int_period
T
INT_PERIOD
(seconds)
7
0.280
6
0.560
5
1.12
4
2.24
3
4.47
2
8.95
1
17.9
0
Disabled
11.4 Enabling the Watchdog Timer
The watchdog timers are free running and require a protected sequence of writes to enable the watchdog timers to prevent
an unintended reset during the enable process.
11.4.1 Enable sequence
1. Write WDT0_RST.wdt_rst: 0x000000A5
2. Write WDT0_RST.wdt_rst: 0x0000005A
3. Set WDT0_CTRL.wdt_en to 1
11.5 Disabling the Watchdog Timer
The watchdog timers can be disabled by the application code manually or by the microcontroller automatically as shown
below.
11.5.1 Manual Disable
Setting WDT0_CTRL.wdt_en to 0 disables the watchdog timer.
11.5.2 Automatic Disable
A power-on-reset (POR) event automatically disables the watchdog timers by setting WDT0_CTRL.wdt_en to 0.
Note: The watchdog timer remains enabled during all other types of reset.
11.6 Resetting the Watchdog Timer
To prevent a watchdog interrupt or a watchdog reset or both, application software must write the reset sequence, shown
below, to the WDT0_RST register prior to an interrupt or reset timeout occurring.
11.6.1 Reset Sequence
1. Write WDT0_RST: 0x0000 00A5
2. Write WDT0_RST 0x0000 005A
11.7 Detection of a Watchdog Reset Event
During system start-up, system software should check the WDT0_CTRL.rst_flag to determine if the reset was the result of a
watchdog reset. Application software is responsible for taking appropriate actions if a watchdog reset occurred.