MAX32660 User Guide
Maxim Integrated Page 17 of 195
3.2.2 SRAM Space
The SRAM area of memory is intended to contain the primary SRAM data memory of the device and is defined from byte
address range 0x2000 0000 to 0x3FFF FFFF (0.5GB maximum). This memory can be used for general purpose variable and
data storage, code execution, and the Arm Cortex-M4 stack.
On the MAX32660, this memory area contains the main system SRAM 96KB, which is mapped from 0x2000 0000 to
0x2001 7FFF.
The entirety of the SRAM memory space on the MAX32660 is contained within the dedicated Arm Cortex-M4
SRAM bit-banding region from 0x2000 0000 to 0x200F FFFF (1MB maximum for bit-banding). This means that the CPU can
access the entire SRAM either using standard byte/word/doubleword access or using bit-banding operations. The bit-
banding mechanism allows any single bit of any given SRAM byte address location to be set, cleared, or read individually by
reading from or writing to a corresponding doubleword (32-bit wide) location in the bit-banding alias area.
The alias area for the SRAM bit-banding is located beginning at 0x2200 0000 and is a total of 32MB maximum, which allows
the entire 1MB bit banding area to be accessed. Each 32-bit (4 byte aligned) address location in the bit-banding alias area
translates into a single bit access (read or write) in the bit-banding primary area. Reading from the location performs a
single bit read, while writing either a 1 or 0 to the location performs a single bit set or clear.
Note: The Arm Cortex-M4 with FPU translates the access in the bit-banding alias area into the appropriate read cycle (for a
single bit read) or a read-modify-write cycle (for a single bit set or clear) of the bit-banding primary area. This means that
bit-banding is a core function (i.e., not a function of the SRAM memory interface layer or the AHB bus layer), and thus is only
applicable to accesses generated by the core itself. Reads/writes to the bit-banding alias area by other (non-Arm -core) bus
masters such as the Standard DMA AHB bus master will not trigger a bit-banding operation and will instead result in an AHB
bus error.
The SRAM area on the MAX32660 is capable code execution. Code stored in the SRAM is accessed directly for execution
using the system bus and is not cached. The SRAM is where the Arm Cortex-M4 stack must be located, as it is the only
general-purpose SRAM memory on the device. A valid stack location inside the SRAM must be set in the vector table stored
at address 0x0000 0000 in the internal flash memory. Refer to the Cortex-M4 with FPU Technical Reference Manual. The
MAX32660 specific AHB Bus Masters can also access the SRAM to use as general storage or working space.
3.2.3 Peripheral Space
The peripheral space area of memory is intended for mapping of control registers, internal buffers/working space, and
other features needed for the firmware control of non-core peripherals. It is defined from byte address range 0x4000 0000
to 0x5FFF FFFF (0.5GB maximum). On the MAX32660, all device-specific module registers are mapped to this memory area,
as well as any local memory buffers or FIFOs which are required by modules.
As with the SRAM region, there is a dedicated 1MB area at the bottom of this memory region (from 0x4000 0000 to
0x400F FFFF) that is used for bit-banding operations by the Arm Cortex-M4 with FPU. Four-byte-aligned read/write
operations in the peripheral bit-banding alias area (32MB in length, from 0x4200 0000 to 0x43FF FFFF) are translated by the
core into read/mask/shift or read/modify/write operation sequences to the appropriate byte location in the bit-banding
area.
Note: The bit-banding operation within peripheral memory space is, like bit-banding function in SRAM space, a core
remapping function. As such, it is only applicable to operations performed directly by the Arm Cortex-M4 core. If another
memory bus master (such as the Standard DMA AHB master) accesses the peripheral bit-banding alias region, the bit-
banding remapping operation will not take place. In this case, the bit-banding alias region will appear to be a non-
implemented memory area (causing an AHB bus error).
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