MAX32660 User Guide
Maxim Integrated Page 185 of 195
14.4 I
2
S Mode
Configure the SPIMSS peripheral for I
2
S mode as follows:
• SPIMSS_CTRL.enable = 0, disable the SPIMSS for SPI and I
2
S.
• SPIMSS_I2S_CTRL.i2s_en = 1, enable I
2
S mode
• SPIMSS_CTRL.phase = 0, set the phase
• SPIMSS_CTRL.clkpol = 0
• SPIMSS_MODE.numbits = 0 (to select 16-bit characters)
• SPIMSS_CTRL.enable = 1
The SPIMSS_CTRL.mmen and SPIMSS_CTRL.ss_io bits are set in accordance with either master or slave mode of operation.
The SPIMSS_MODE.ssv bit is ignored by hardware in I
2
S mode. In I
2
S, the master hardware sources the word select pin,
I2S_BCLK, and the left-right clock pin, I2S_LRCLK. In I
2
S mode, the word select signal toggles between consecutive audio
words. I2S_LRCLK is low for the left channel data and is high for the right channel data.
The receive and/or transmit DMA channels must be enabled when operating in I
2
S mode. Typically, audio data will only flow
in one direction as defined by the SPIMSS_DMA.rx_dma_en or SPIMSS_DMA.tx_dma_en bits, however audio data may be
transferred in both directions simultaneously if desired. Data in the transmit buffer should be initialized with the first 16-bit
character containing a left channel audio sample, then alternating right and left channel 16-bit audio samples. When audio
data is being received, the first sample written into the receive buffer will be a left channel audio sample.
14.4.1 Mute
The SPIMSS_I2S_CTRL.i2s_mute bit in the I
2
S Control Register can be set by software asynchronously to the DMA transfers
to silence the transmit output. At the beginning of the next left channel audio sample after SPIMSS_I2S_CTRL.i2s_mute is
asserted, DMA and FIFO accesses will continue, however, the data read from the transmit FIFO will be discarded and
replaced with zeroes. When SPIMSS_I2S_CTRL.i2s_mute is deasserted, the transmit output will resume at the beginning of
the next left channel audio sample.
14.4.2 Pause
The SPIMSS_I2S_CTRL.i2s_pause bit can be set by software asynchronously to the DMA transfers to halt DMA and FIFO
accesses. At the beginning of the next left channel audio sample after SPIMSS_I2S_CTRL.i2s_pause is set to 1, both transmit
and receive DMA and FIFO accesses will halt and the transmit data will be forced to zero. At the beginning of the next left
channel audio sample after SPIMSS_I2S_CTRL.i2s_pause is set to 0, the DMA accesses will resume from the position at
which the pause occurred. Pause takes precedence over mute.
14.4.3 Mono
The SPIMSS_I2S_CTRL.i2s_mono bit in the I
2
S Control Register is set to select single channel audio data vs. stereo format. In
mono mode each transmit data word read from the transmit FIFO is duplicated for both left and right channel output
words. The receive channel will read the data from the left channel (I2S_LRCLK pin low) and ignore data in the right channel
(I2S_LRCLK pin high). This allows DMA buffers for mono mode to be one-half the size of DMA buffers for stereo mode.
14.4.4 Left Justify
The SPIMSS_I2S_CTRL.i2s_lj bit selects the phase of the I2S_LRCLK signal versus the data. When SPIMSS_I2S_CTRL.i2s_lj = 0
(normal I
2
S mode), the audio data lags the transition of the I2S_LRCLK signal by one I2S_BCLK period as shown in Figure
14-3, below. When SPIMSS_I2S_CTRL.i2s_lj = the most significant bit of the
channel audio data is available when the I2S_LRCLK signal transitions.
To Next Page
Loading...
