Maxim Integrated MAX32660 - Page 22

MAX32660 User Guide
Maxim Integrated Page 22 of 195
The following steps describe how to change the OVR:
1. Ensure the part is operating from the internal LDO for V
CORE
.
a. Set PWRSEQ_LP_CTRL.ldo_dis to 0.
b. If using an external supply for V
CORE
, ensure the external supply is set to the same voltage as the current OVR
setting. The external supply must be equal to or greater than the set OVR voltage.
2. Set either the 32.768kHz external oscillator or 8kHz nano-ring oscillator as the system clock source.
a. Refer to section 4.3 Oscillator Sources and System Clock Selection for details on system clock selection.
3. Set the number of Flash Wait States to the POR default value of 5.
a. GCR_MEM_CTRL.fw = 5
4. Change the OVR setting to the desired range.
a. Set PWRSEQ_LP_CTRL.ovr to either 0, 1, or 2 as shown in Table 4-1, above.
5. Set the Flash Low Voltage Enable according to the OVR setting set in step 4.a.
a. Set FLC_CTRL.lve to either 0 or 1 as required. Reference Table 4-1, above for the required value.
6. If desired, set the system clock source to the HFIO and update the system clock prescaler to the desired value.
a. Set GCR_CLK_CTRL.clksel = 0.
b. Wait for the system clock ready bit, GCR_CLK_CTRL.clkrdy, to read 1.
c. Set GCR_CLK_CTRL.psc to the desired prescaler value.
7. Set the number of Flash Wait States per Table 4-2, below.
a. Set GCR_MEM_CTRL.fws to the minimum value shown for the selected OVR and System Clock
8. Perform a Peripheral Reset.
a. Set GCR_RST0.periph_rst = 1.
On each subsequent reset event:
1. If PWRSEQ_LP_CTRL.ovr is set to 0, set the flash low voltage enable bit to 1 (FLC_CTRL.lve = 1)
2. Set the clock prescaler, GCR_CLK_CTRL.psc, as needed by the system.
3. Set the number of flash wait states, GCR_MEM_CTRL.fws, as needed based on the OVR settings using Table 4-2,
below.
4.1.2 Flash Wait States
Power-On Reset, System Reset and Watchdog Reset all reset the Flash Wait State field, GCR_MEM_CTRL.fws, to the POR
default setting of 5. The Flash Wait State field is the number of system clock cycles for accessing the internal flash memory
and is dependent on the OVR settings, the system oscillator selected and the system oscillator prescaler.
The setting for the number of flash wait states effects performance and it is critical to set it correctly based on the OVR
settings and the system clock frequency. Set the number of flash wait states using the field GCR_MEM_CTRL.fws per Table
4-2, below. The GCR_MEM_CTRL.fws field should always be set to the default POR reset value of 5 prior to changing the
PWRSEQ_LP_CTRL.ovr settings.
Important: Flash reads may fail and result in unknown instruction execution if the Flash Wait State setting is lower than the
minimum required for a given OVR setting and the selected system clock frequency.