MAX32660 User Guide
Maxim Integrated Page 27 of 195
For the low power modes, the Arm Cortex-M4 with FPU does not execute code. Each low power mode of operation
supports wakeup events that result in the MAX32660 to re-enter ACTIVE mode operation. For SLEEP mode, wakeup events
include any external or internal interrupt, RTC wakeup, and the Watchdog Interrupt. DEEPSLEEP and BACKUP mode wakeup
events are limited to any enabled GPIO external interrupt or from an enabled RTC wakeup event.
The Arm Cortex-M family of CPUs have two built-in low power modes, designated SLEEP and DEEPSLEEP. Implementation of
these low-power modes are speci Arm Cortex-M4
with FPU System Control Register (SCR). Write register bit SCR.deepsleep to select the low power mode as shown in the
pseudocode below.
SCR.sleepdeep = 0; // SLEEP mode enabled
SCR.sleepdeep = 1; // DEEPSLEEP mode enabled
Once enabled, the device enters the enabled low power mode when either a WFI (Wait for Interrupt) or WFE (Wait for
Event) instruction is executed.
Immediately before entering any low-power mode, enable the SYSOSC to be used in that low-power mode. If the selected
SYSOSC is disabled in the selected low power mode, it will be enabled upon returning to ACTIVE mode.
Refer to the Cortex-M4 with FPU Technical Reference Manual for more information on the SCR register and the WFI and
WFE instructions.
4.5.1 ACTIVE Mode
This is the highest performance mode. All internal clocks, registers, memory, and peripherals are enabled. The CPU is
running and executing application code. All oscillators are available for application use, if enabled.
Dynamic clocking allows firmware to selectively enable or disable clocks and power to individual peripherals, providing the
optimal mix of high-performance and power conservation. Internal RAM that can be enabled, disabled, or placed in low-
power RAM Retention Mode include data SRAM memory blocks, on-chip cache, and on-chip FIFOs. Refer to RAM Low
Power Modes for details on RAM power mode control.
4.5.2 SLEEP Low Power Mode
This is a low power mode that suspends the CPU with a fast wakeup time to ACTIVE mode. In SLEEP mode, the
microcontroller remains in an ACTIVE state with the system clock disabled for the Cortex core. Code execution stops during
SLEEP mode. All enabled oscillators remain active and the RAM retains state if enabled. Refer to RAM Low Power Modes for
details on enabling and disabling RAM sector data retention.
SLEEP mode wakeup events include any external or internal interrupt.
The following pseudocode places the device in SLEEP mode:
GCR_PMR.mode = 0; // Set mode field to ACTIVE to ensure DEEPSLEEP mode is entered
SCR.sleepdeep = 0; // SLEEP mode enabled
WFI; // Enter SLEEP mode, WFI can be replaced with WFE
Refer to the Cortex-M4 with FPU Technical Reference Manual for more information on the SCR register and the WFI and
WFE instructions.
4.5.3 DEEPSLEEP Low Power Mode
In DEEPSLEEP mode all internal clocks are gated off including the system clock and the Watchdog Timer. The RTC continues
operation, if enabled, during DEEPSLEEP. The Arm Cortex-M4 with FPU state and all system and peripheral registers retain
To Next Page
Loading...
