Maxim Integrated MAX32660 - Page 30

MAX32660 User Guide
Maxim Integrated Page 30 of 195
Peripheral
Reset
Soft
Reset
System
Reset
POR
ACTIVE
Mode
SLEEP
Mode
DEEPSLEEP
Mode
BACKUP
Mode
8kHz Osc
On
On
On
On
On
On
On
On
High Freq Osc
-
-
On
On
Y
Y
Auto Off
Off
PCLK
On
On
On
On
On
On
Off
Off
HCLK
On
On
On
On
On
On
Off
Off
CPU Clock
On
On
On
On
On
Off
Off
Off
V
CORE
On
On
On
On
On
On
Off
Off
CPU State Retention
On
On
Reset
Reset
N/A
On
On
Off
RTC
-
-
Reset
Reset
Y
Y
Y
Y
Standard DMA
Reset
Reset
Reset
Reset
Y
Y
Off
Off
Watchdog Timer
-
-
Reset
Reset
Y
Y
Off
Off
GPIO
-
Reset
Reset
Reset
Y
Y
Y
Y
Flash Controller,
ICC0 Cache
Reset
Reset
Reset
Reset
Y
Y
Off
Off
Other Peripherals
Reset
Reset
Reset
Reset
Y
Y
Off
Off
AoD
On
Y
Y
Y
Y
On
On
Auto Off
RAM Retention
Y
Y
Y
Reset
Y
Y
Y
Auto Off
Table key:
Y = Enabled, can be disabled by firmware
On = Enabled by hardware (Cannot be disabled)
Off = Disabled by hardware (Cannot be enabled)
Auto Off = Can either be left on, or automatically gated off when in this power mode.
- = No Effect
N/A = Not Applicable
Note: The AoD includes the oscillator trim settings, the RTC, RAM retention, and Low Power Wakeup Control Registers.
Note: Only a Power-On Reset triggers a reset of the AoD.
Note: RAM Retention applies to data SRAM, cache, and all FIFOs.
Note: Peripheral, Soft, and System Resets are initiated by firmware though the GCR_RST0 register.
Note: A Watchdog Reset initiates a System Reset.
4.8 Instruction Cache Controller
ICC0 is the Instruction Cache Controller used for the internal Flash Memory. ICC0 includes a line buffer, tag RAM and a 16KB
2-way set associative Data RAM.
4.8.1 Enabling ICC0
Perform the following steps to enable ICC0.
• Set ICC0_CACHE_CTRL.enable to 1
• Read ICC0_CACHE_CTRL.ready until it returns 1
4.8.2 Disabling ICC0
Disable ICC0 by setting ICC0_CACHE_CTRL.enable to 0.