Maxim Integrated MAX32660 - Page 37

MAX32660 User Guide
Maxim Integrated Page 37 of 195
System Clock Control Register
GCR_CLK_CTRL
[0x0008]
Bits
Name
Access
Reset
Description
25
x32k_rdy
RO
0
32.768kHz External Oscillator Ready Status
On POR or System Reset this field is set to 0. Setting GCR_CLK_CTRL.x32k_en to 1 forces this
field to 0 and hardware sets this field to 1 automatically when the oscillator is ready for use.
0: Oscillator not ready.
1: Oscillator ready.
24:19
-
RO
-
Reserved for Future Use
Do not modify this field.
18
hirc_en
R/W
1
High-Frequency Internal Oscillator (HFIO) Enable
Write 0 to disable the internal HFIO. When this field is set to 0, hardware automatically
clears the GCR_CLK_CTRL.hirc_rdy bit.
0: Set to 0 to disable the HFIO.
1: Set to 1 to enable the HFIO.
17
x32k_en
R/W
0
32.768kHz External Oscillator Enable
Write 1 to enable the 32kHz external oscillator. After setting this field to 1, hardware
automatically clears GCR_CLK_CTRL.x32k_rdy. When the GCR_CLK_CTRL.x32k_rdy bit reads
1, the 32.768kHz oscillator is ready.
0: Disable the 32kHz oscillator (POR default).
1: Enable the 32kHz oscillator.
16:14
-
RO
-
Reserved for Future Use
Do not modify this field.
13
clkrdy
R/W
0
System Oscillator Clock Source Ready
When the System Oscillator source is modified by changing the GCR_CLK_CTRL.clksel field,
the GCR_CLK_CTRL.clkrdy field reads 0 until the switchover completes. This field is set to 1
by hardware when the selected clock source is ready.
0: The selected System Oscillator is not ready for use.
1: The selected clock source (GCR_CLK_CTRL.clksel) is the active System Oscillator.
12
-
RO
-
Reserved for Future Use
Do not modify this field.
11:9
clksel
R/W
0
System Oscillator Source Select
Selects the system oscillator (SYSOSC) source used to generate the system clock (SYSCLK).
Modifying this field immediately clears the GCR_CLK_CTRL.clkrdy field.
0: High-Frequency Internal Oscillator (HFIO)
1: Reserved for Future Use
2: Reserved for Future Use
3: 8kHz Low-Frequency Internal Oscillator
4: Reserved for Future Use
5: Reserved for Future Use
6: 32.768kHz External Oscillator
7: Reserved for Future Use
8:6
psc
R/W
0
System Oscillator Prescaler
Sets the divider for generating the System Clock (SYSCLK) from the selected System
Oscillator (SYSOSC) as shown in the following equation:







5:0
-
R/W
8
Reserved for Future Use
Do not modify this field.