MAX32660 User Guide
Maxim Integrated Page 75 of 195
To configure a channel for buffer chaining, initialize the following registers:
• DMAn_CFG
• DMAn_SRC
• DMAn_DST
• DMAn_CNT
• DMAn_SRC_RLD
• DMAn_DST_RLD
• DMAn_CNT_RLD
When the DMAn_CNT_RLD register is written, the DMAn_CNT_RLD.rlden bit must not be set. In addition, any writes to the
DMAn_CFG register prior to initialization must not set the DMAn_CFG.chen and DMAn_CFG.rlden bits. After all registers are
initialized, the last operation involves writing to the DMAn_CFG.chen and DMAn_CFG.rlden bits. This starts the DMA.
Set the DMAn_CFG.ctzien bit in the register to receive an interrupt after each buffer is accessed. In addition, set the
DMAn_CFG.chdien bit to provide an interrupt in case of a bus error.
Caution: Setting the DMAn_CFG.chen and the DMAn_CFG.rlden bits separately risks a race condition. The condition occurs
between a DMA completion interrupt service routine initializing the reload registers for the third buffer before the software
initialization of these registers for the second buffer.
When the first DMA transfer completes (based on the DMAn_CNT.cnt bit value), a CTZ interrupt occurs, and the
DMAn_SRC, DMAn_DST, and DMAn_CNT registers are reloaded from the corresponding reload registers.
The DMAn_STAT register indicates that the reload and CTZ events occurred. In this case, DMAn_STAT.ch_st = 1 indicating
that the DMA is now busy with the second DMA transfer defined in the reload registers. If DMAn_STAT.ch_st = 0, then the
initial and second DMA transfers have completed. If there are additional buffers to chain, the interrupt service routine
initializes the DMAn_SRC_RLD, DMAn_DST_RLD, and DMAn_CNT_RLD registers and sets the DMAn_CNT_RLD.rlden bit. The
interrupt service routine does not write to the DMAn_CFG, DMAn_SRC, DMAn_DST, and DMAn_CNT registers, just the
reload registers.
To prevent improper operation, program the address bits before setting the DMAn_CFG.chen and DMAn_CNT_RLD.rlden
bits.
7.8 DMA Interrupts
Enable interrupts for each channel by setting DMA_INT_EN.chien. When an interrupt is pending, the corresponding
DMA_INT_FL.ipend = 1. The DMA_INT_FL.ipend field is read-only, to clear the interrupt use the DMAn_STAT register and
write a 1 to the field that indicates the cause of the interrupt.
A channel interrupt (DMAn_STAT.ipend = 1) is caused by:
1. DMAn_CFG.ctzien = 1
a. If enabled, all CTZ occurrences set the DMAn_STAT.ipend bit.
2. DMAn_CFG.chdien = 1
a. If enabled, any clearing of the DMAn_STAT.ch_st bit sets the DMAn_STAT.ipend bit. Examine the DMAn_STAT
register to determine which reason caused the disable. The DMAn_CFG.chdien bit also enables the
DMAn_STAT.to_st bit. The DMAn_STAT.to_st bit does not clear the DMAn_STAT.ch_st bit.
To clear the channel interrupt, write 1 to the cause of the interrupt (the DMAn_STAT.ctz_st, DMAn_STAT.rld_st,
DMAn_STAT.bus_err, or DMAn_STAT.to_st bits).
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