Maxim Integrated MAX32660

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MAX32660 User Guide

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UART TX FIFO Data Output Register

UARTn_TXFIFO

[0x0024]

Bits

Name

Access

Reset

Description

7:0

data

TX FIFO Data Output Peek Register

Reads from this register return the next character available for transmission at the end

of the TX FIFO. If no data is available, 0x00 is returned.

Reads from this register do not affect the TX FIFO state.

Main Page

Table of Contents8
Introduction13
Overview13
Figure 2-1: MAX32660 High Level Block Diagram14
Figure 3-1: Code Memory Mapping15
Memory, Register Mapping, and Access15
Figure 3-2: Data Memory Map16
Table 3-1: APB Peripheral Base Address Map19
Table 4-1: Operating Voltage Range Selection and the Effect on V21
System Clocks, Reset, and Power Management21
Table 4-2: Minimum Flash Wait State Setting for each OVR Setting23
Figure 4-1: Clock Tree Diagram24
Table 4-3: Reset Sources and Effect on Oscillator Status25
Table 4-4: Reset Sources and Effect on System Oscillator Selection and Prescaler25
Table 4-5: Wake-Up Sources for each Low-Power Mode28
Table 4-6: Reset and Low Power Mode Effects29
Table 4-7: Instruction Cache Controller Register Addresses and Descriptions31
Table 4-8: ICC Cache ID Register31
Table 4-9: ICC Memory Size Register31
Table 4-10: ICC Cache Control Register32
Table 4-11: ICC Invalidate Register32
Table 4-12: Global Control Registers, Offsets and Descriptions33
Table 4-13: System Control Register33
Table 4-14: Reset 0 Register34
Table 4-15: System Clock Control Register36
Table 4-16: Power Management Register38
Table 4-17: Peripheral Clock Disable 0 Register38
Table 4-18: Memory Clock Control Register40
Table 4-19: Memory Zeroization Control Register42
Table 4-20: System Status Flag Register42
Table 4-21: Reset Register 143
Table 4-22: Peripheral Clock Disable Register 143
Table 4-23: Event Enable Register44
Table 4-24: Revision Register44
Table 4-25: System Status Interrupt Enable Register44
Table 4-26: System Initialization Registers, Offsets and Descriptions44
Table 4-27: Function Control Register 045
Table 4-28: System Initialization Address Error Register45
Table 4-29: Function Control Registers, Offsets and Descriptions45
Table 4-30: Function Control Register 045
Table 4-31: Power Sequencer Low Power Control Registers, Offsets, Access and Descriptions46
Table 4-32: Low Power Voltage Control Register47
Table 4-33: Low Power Mode Wakeup Flags for GPIO049
Table 4-34: Low Power Wakeup Enable for GPIO0 Register49
Table 4-35: RAM Shut down Register49
Table 5-1: Internal Flash Memory Organization51
Table 5-2: Valid Addresses for 32-Bit and 128-Bit Internal Flash Writes52
Table 5-3: Page Boundary Address Range for Page Erase Operations53
Table 5-4: Flash Controller Registers, Offsets, Access and Descriptions54
Table 5-5: Flash Controller Interrupt Register56
Table 5-6: Flash Controller Data Register 057
Table 5-7: Flash Controller Data Register 157
Table 5-8: Flash Controller Data Register 257
Table 5-9: Flash Controller Data Register 357
Table 6-2: GPIO Port, Pin Name and Alternate Function Matrix, 20-TQFN59
Table 6-1: GPIO Port, Pin Name and Alternate Function Matrix, 16-WLP59
Table 6-3: Standard GPIO Drive Strength Selection61
Table 6-4: GPIO with I 2 C Alternate Function Drive Strength Selection61
Table 6-5: GPIO Mode and Alternate Function Selection61
Table 6-6: GPIO Port Interrupt Vector Mapping62
Table 6-7: GPIO Wakeup Interrupt Vector62
Table 6-8: GPIO Port 0 Registers63
Table 6-9: GPIO Alternate Function 0 Select Register63
Table 6-10: GPIO Output Enable Register64
Table 6-11: GPIO Output Register64
Table 6-12: GPIO Input Register65
Table 6-13: GPIO Port Interrupt Mode Register65
Table 6-14: GPIO Port Interrupt Polarity Registers65
Table 6-15: GPIO Port Interrupt Enable Registers65
Table 6-16: GPIO Interrupt Flag Register66
Table 6-17: GPIO Wakeup Enable Registers66
Table 6-18: GPIO Interrupt Dual Edge Mode Registers66
Table 6-19: GPIO Pullup/Pulldown Enable Register67
Table 6-20: GPIO Alternate Function Select Register67
Table 6-21: GPIO Input Hysteresis Enable Register67
Table 6-22: GPIO Slew Rate Enable Register67
Table 6-23: GPIO Drive Strength 0 Select Register68
Table 6-24: GPIO Drive Strength 1 Select Register69
Table 6-25: GPIO Pullup/Pulldown Select Register70
Figure 7-1: DMAC Block Diagram71
Table 7-1: DMA Channel Registers71
Table 7-2: Channel Reload Registers72
Table 7-3: Source and Destination Address Definition73
Table 7-4: Data Movement from Source to DMA FIFO73
Table 7-5: Data Movement from the DMA FIFO to Destination74
Table 7-6: Standard DMA Control Registers, Offsets, Access and Descriptions77
Table 7-7: DMA Interrupt Enable Register77
Table 7-8: DMA Interrupt Flag Register77
Table 7-9: Standard DMA Channel 0 to Channel 15 Offsets78
Table 7-10: Dman Channel Registers, Offsets, Access and Descriptions78
Table 7-11: DMA Configuration Register79
Table 7-12: DMA Status Register81
Table 7-13: DMA Source Register82
Table 7-14: DMA Destination Register82
Table 7-15: DMA Count Register82
Table 7-16: DMA Source Reload Register83
Table 7-17: DMA Destination Reload Register83
Table 7-18: DMA Count Reload Register83
Table 8-1: Example Baud Rate Calculation Results, Target Bit Rate = 1.8Mbps, F86
Table 8-2: UART Registers, Offset Addresses and Descriptions87
Table 8-3: UART Control 0 Register87
Table 8-4: UART Control 1 Register89
Table 8-5: UART Status Register90
Table 8-6: UART Interrupt Enable Register91
Table 8-7: UART Interrupt Flags Register92
Table 8-8: UART Rate Integer Register93
Table 8-9: UART Baud Rate Decimal Register93
Table 8-10: UART FIFO Register94
Table 8-11: UART DMA Configuration Register94
Table 8-12: UART TX FIFO Data Output Register94
Figure 9-1. RTC Block Diagram97
Table 9-1. RTC Registers, Offsets and Descriptions100
Table 9-2: RTC Seconds Counter Register100
Table 9-3: RTC Sub-Seconds Counter Register101
Table 9-4: RTC Sub-Seconds Counter Register101
Table 9-5: RTC Sub-Second Alarm Register101
Table 9-6: RTC Control Register101
Table 9-7: RTC Trim Register103
Figure 10-1: One-Shot Mode Diagram107
Figure 10-2: Continuous Mode Diagram109
Figure 10-3: Counter Mode Diagram111
Figure 10-4: Capture Mode Diagram115
Figure 10-5: Counter Mode Diagram117
Figure 10-6: Gated Mode Diagram119
Table 10-1: Timer Register Offsets, Names, Access and Descriptions122
Table 10-2: Timer Count Registers122
Table 10-3: Timer Compare Registers122
Table 10-4: Timer PWM Registers123
Table 10-5: Timer Interrupt Registers123
Table 10-6: Timer Control Registers123
Figure 11-1: Watchdog Timer Block Diagram126
Table 11-1: Watchdog Timer Interrupt Period with F127
Table 11-2: Watchdog Timer Registers129
Table 11-3: Watchdog Timer Control Register129
Table 11-4: Watchdog Timer Reset Register130
Table 12-1: I 2 C Bus Terminology131
Figure 12-1: the Roles of I C Devices and the Direction the I C Signals132
Figure 12-2: I C Write Data Transfer134
Figure 12-3: I C Specification Minimum and Maximum Clock Parameters for Standard and Fast Mode136
Table 12-2: I C Address Byte Format138
Figure 12-4: I C Clock Period142
Table 12-3: I C Registers144
Table 12-4: I 2 C Control Registers 0145
Table 12-5: I C Status Registers147
Table 12-6: I 2 C Interrupt Status Flags Registers 0148
Table 12-7: I C Interrupt Enable 0 Registers150
Table 12-8: I C Interrupt Status Flags 1 Registers151
Table 12-9: I 2 C Interrupt Enable Registers 1151
Table 12-10: I C FIFO Length Registers152
Table 12-11: I 2 C Receive Control Registers 0152
Table 12-12: I C Receive Control 1 Registers153
Table 12-13: I 2 C Transmit Control Registers 0153
Table 12-14: I 2 C Transmit Control Registers 1154
Table 12-15: I C Data Registers155
Table 12-16: I C Master Mode Control Registers155
Table 12-17: I C SCL Low Control Register156
Table 12-18: I C SCL High Control Register156
Table 12-19: I C Timeout Registers156
Table 12-20: I C Timeout Registers157
Table 12-21: I C Slave Address Register157
Table 12-22: I C DMA Register158
Figure 13-1: SPI0 Block Diagram159
Figure 13-2: 4-Wire SPI Connection Diagram160
Table 13-1: Four-Wire SPI Signals160
Figure 13-3: 3-Wire SPI Connection Diagram161
Table 13-2: Three-Wire SPI Signals161
Table 13-3: SPI0 Pins162
Figure 13-4: SCK Clock Rate Control163
Table 13-4. Clock Phase and Polarity Operation164
Figure 13-5: SPI Clock Polarity164
Figure 13-6. SPI Timing (Spi0_Ctrl2.Clk_Pha = 0)165
Figure 13-7. SPI Timing (Spi0_Ctrl2.Clk_Pha = 1)166
Figure 13-8: Three-Wire SPI Read167
Figure 13-9: Three-Wire SPI Write167
Table 13-5: SPI0 Master Register Addresses and Descriptions169
Table 13-6: SPI FIFO Data Registers169
Table 13-7: SPI Master Signals Control Registers169
Table 13-8: SPI Transmit Packet Size Register171
Table 13-9: SPI Static Configuration Registers171
Table 13-10: SPI Slave Select Timing Register172
Table 13-11: SPI Master Clock Configuration Registers172
Table 13-12: SPI DMA Control Registers173
Table 13-13: SPI Interrupt Flag Registers174
Table 13-14: SPI Interrupt Enable Registers176
Table 13-15: SPI Wakeup Status Flags Registers177
Table 13-16: SPI Wakeup Enable Registers177
Table 13-17: SPI Status Registers177
Table 14-1: Four-Wire SPI Signals179
Figure 14-1. SPIMSS Block Diagram179
Table 14-2: I S Signals180
Figure 14-2: 4-Wire SPI Connection Diagram180
Table 14-3: SPIMSS Pins for SPI1 and I 2 S181
Table 14-4. Clock Phase and Polarity Operation182
Figure 14-3: I S Audio Data in Standard I S Operation186
Figure 14-4: I S Mode (I2S_En=1, I2S_Lj=1)186
Table 14-5: SPIMSS Register Offsets, Access and Descriptions189
Table 14-6. SPIMSS Data Register189
Table 14-7: SPIMSS Control Register189
Table 14-8: SPIMSS Interrupt Flag Register190
Table 14-9: SPIMSS Mode Register191
Table 14-10: SPIMSS Bit Rate Generator Register192
Table 14-11: SPIMSS DMA Register192
Table 14-12: SPIMSS I 2 S Control Register194

Maxim Integrated MAX32660 - Page 95

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