MAX32660 User Guide
Maxim Integrated Page 99 of 195
9.3.1 RTC Register Write Protection
The RTC_CTRL.busy bit is a read-only status bit controlled by hardware and set when any of the following conditions occur:
• System Reset.
• Software writes to the RTC_SEC register or RTC trim registers.
• Software modifies the RTC_CTRL.enable, RTC_CTRL.alarm_tod_en, or RTC_CTRL.alarm_ss_en bits.
When the RTC_CTRL.busy bit is set by hardware, writes to the above RTC control bits and count registers are blocked by
hardware. The RTC_CTRL.busy bit remains active until the register or bit is synchronized by hardware. The synchronization
by hardware occurs on the next rising edge of the 32kHz clock. The RTC_CTRL.busy bit is set for a maximum of one 4kHz
clock, approximately Therefore, a software write is not complete until hardware clears the RTC_CTRL.busy bit
indicating that a 32kHz synchronized version of the registers and bit are in place.
Once the RTC_CTRL.busy bit is cleared to 0, additional writes are completed as permitted by individual count or alarm-
enable bits.
9.3.2 RTC Register Read Protection
The Ready (RTC_CTRL.ready) bit indicates when the RTC count registers contain valid data. Hardware clears the
RTC_CTRL.ready bit approximately one 4kHz clock before the ripple occurs through the RTC counter registers (RTC_SEC and
RTC_SSEC) and is set once again immediately after the ripple occurs. The period of the RTC_CTRL.ready bit set/clear activity
is approximately 3.9 msec, providing a large window during which the RTC count registers are readable. Software can clear
the RTC_CTRL.ready bit at any time and the bit remains clear until set by hardware when the next ripple occurs. A separate
Ready Enable (RTC_CTRL.ready_int_en) bit is provided to generate an interrupt when hardware sets the RTC_CTRL.ready
bit. You can use this interrupt to signal the start of a new RTC read window.
9.3.3 RTC Count Register Access
The RTC count registers (RTC_SEC and RTC_SSEC) are readable when the RTC_CTRL.ready bit is set to 1. Data read from
these registers when RTC_CTRL.ready is 0 is invalid. To write the RTC count registers, set the RTC Enable (RTC_CTRL.enable)
bit to 0. Clearing the RTC_CTRL.enable bit is permitted only when the Write Enable (RTC_CTRL.write_en) bit is set to 1 and is
governed by the RTC_CTRL.busy bit signaling process (that is, the RTC_CTRL.busy bit is 0). Writes to each RTC count register
must occur only when the RTC_CTRL.busy bit reads 0.
9.3.4 RTC Alarm Register Access
The RTC alarm registers (RTC_RAS and RTC_RSSA) are readable at any time. To write to an alarm register, disable the
corresponding alarm enable first (RTC_CTRL.alarm_ss_en = 0 or RTC_CTRL.alarm_tod_en = 0). Clearing these bits requires
monitoring the RTC_CTRL.busy bit to assess completion of the write. Once the alarm is disabled, update the associated RTC
alarm registers using software.
9.3.5 RTC Trim Register Access
The RTC Trim register (RTC_TRIM) is readable at any time. To write to this register, set the Write Enable
(RTC_CTRL.write_en) bit to 1 and check the RTC_CTRL.busy bit until it reads 0 and then write the RTC_TRIM register.
9.3.6 RTC Oscillator Control Register Access
The RTC oscillator control register (RTC_OSCCTRL) is readable at any time. To write to this register, set the Write Enable
(RTC_CTRL.write_en) bit to 1 and check the RTC_CTRL.busy bit until it reads 0 and then write to the RTC_OSCCTRL register.
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