Phoenix Contact PSRmodular - Figure 5-149: Duty Cycle Examples for HIGH to LOW

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PHOENIX CONTACT 109241_en_03

Duty cycle choice Up to seven inputs can be selected for seven different duty cycles of the output signal.

Depending on the active input, the clock signal has a corresponding duty cycle at “O

UT”.

The “I

N” input must always be set to logic “1”. The table below shows the method of opera-

tion of the “CLOCKING” operator.

Figure 5-149 Duty cycle examples for HIGH to LOW

Duty cycle

EN IN 10% IN 20% IN 30% IN 40% IN 60% IN 70% IN 80% OUT

0 0 0 0 0 0 0 0 0

1 0 0 0 0 0 0 0 50%

1 1 0 0 0 0 0 0 10%

1 0 1 0 0 0 0 0 20%

1 0 0 1 0 0 0 0 30%

1 0 0 0 1 0 0 0 40%

1 0 0 0 0 1 0 0 60%

1 0 0 0 0 0 1 0 70%

1 0 0 0 0 0 0 1 80%

1 1 0 0 0 0 0 1 90%

– To generate the desired clock signal at the “O

UT” output, the “EN” input and a clock

signal must be selected (controlled) at the “I

N x%” input.

– The clock signal generation for the 90% duty cycle can only be achieved through the

parallel control of both the “I

N 10%” input and the “IN 80%” input.

– If more than one clock signal input is controlled, the “O

UT” output generates a duty cy-

cle of 50% (exception: “I

N 10%” and “IN 80%”).

DUTY CYCLE 50%

DUTY CYCLE 20%

DUTY CYCLE 40%

DUTY CYCLE 80%

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