R&S ZNL Series - Page 638

Command reference
R&S
®
ZNL/ZNLE
638User Manual 1178.5966.02 ─ 20
Bit No. Meaning
2 HARDware register summary
This bit is set if a bit is set in the STATus:QUEStionable:INTegrity:HARDware register and
the associated ENABle bit is set to 1.
STATus:QUEStionable:INTegrity:HARDware
The STATus:QUEStionable:INTegrity:HARDware register can be queried using
the commands STATus:QUEStionable:INTegrity:HARDware:CONDition? or
STATus:QUEStionable:INTegrity:HARDware[:EVENt]?
The bits in the STATus:QUEStionable:INTegrity:HARDware register are defined
as follows.
Bit No. Meaning
0 Not used
1 Reference frequency lock failure
If an external reference signal or an internal high precision clock (option B4) is used, the
local oscillator is phase locked to a reference signal. This bit is set if this phase locked
loop (PLL) fails.
For external reference: check frequency and level of the supplied reference signal.
2 Output power unleveled
This bit is set if the level control at one of the ports is unsettled or unstable, possibly due to
an external disturbing signal.
Change generator level at the port; check external components.
3 Receiver overload protection tripped
This bit is set if the analyzer detects an excessive input level at one of the ports. If this
condition persists, all internal sources are switched off.
Reduce RF input level at the port. Check amplifiers in the external test setup, then switch
on the internal source using OUTPut ON.
6 Internal communication error
This bit is set if an internal error caused the analyzer to perform an automatic hardware
reset. The current measurement results are possibly invalid.
The bit is automatically cleared at the beginning of the next sweep, no action is required.
7 Instrument temperature is too high
This bit is set if the analyzer detects that the instrument temperature is too high.
Reduce ambient temperature, keep ventilation holes of the casing unobstructed.
8 OCXO cold
This bit is set if the oven for the internal high precision clock (option B4) is not at its operat-
ing temperature.
Wait until the oven has been heated up.
9 Unstable level control
This bit is set if the analyzer detects an excessive source level at one of the ports. The
signal is turned off and the sweep halted.
Check signal path for the received wave, especially check external components. Then
restart the sweep (INITiate<Ch>[:IMMediate]).
VNA remote control basics