Remote Control
R&S
®
FSVA/FSV
598Operating Manual 1176.7510.02 ─ 09
Bit No. Meaning
4 LMARgin 5 FAIL
This bit is set if limit margin 5 is violated.
5 LMARgin 6 FAIL
This bit is set if limit margin 6 is violated.
6 LMARgin 7 FAIL
This bit is set if limit margin 7 is violated.
7 LMARgin 8 FAIL
This bit is set if limit margin 8 is violated.
8 to 14 Not used
15 This bit is always 0.
STATus:QUEStionable:POWer Register
The STATus:QUEStionable:POWer register contains information about possible over-
load situations that may occur during operation of the R&S FSVA/FSV.
You can read out the register with STATus:QUEStionable:POWer:CONDition? or
STATus:QUEStionable:POWer[:EVENt]?
Table 4-11: Meaning of the bits used in the STATus:QUEStionable:POWer register
Bit No. Meaning
0 OVERload
This bit is set if an overload occurs at the RF input.
The R&S FSVA/FSV displays the enhancement label "OVLD".
1 UNDerload
This bit is set if an underload occurs at the RF input.
The R&S FSVA/FSV displays the enhancement label "UNLD".
2 IF_OVerload
This bit is set if an overload occurs in the IF path.
The R&S FSVA/FSV displays the enhancement label "IFOVL".
3 to 14 Unused
15 This bit is always 0.
STATus:QUEStionable:SYNC Register
This register contains information about the state of the I/Q data acquisition. This regis-
ter is used with option Digital Baseband Interface (R&S FSV-B17).
The status of the STATus:QUESTionable:SYNC register is indicated in bit 11 of the
STATus:QUESTionable register.
You can read out the state of the register with STATus:QUEStionable:SYNC:
CONDition? on page 880 and STATus:QUEStionable:SYNC[:EVENt]?
on page 880.
Remote Control - Basics
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