Anritsu ML2437A - Message Available Bit (MAV)

GPIB Operation 488.2 Command Format
ML2437A/38A OM/PM PN: 10585-00001 Rev. P 8-7
If an event causes a bit in the ESR to be set and the corresponding bit in the Event Status
Enable byte (ESE) is set, the ESB bit in the status byte will be set. This can cause an SRQ
(see Section 6-8) if the ESB bit in the Status Register Enable byte (SRE) is set. For example,
to get an SRQ on an unrecognized command do the following:
1. Set the CMD bit in the event status enable byte, and set the ESB bit in the status
register enable byte. Send:
*ESE 32;*SRE 32
2. Now if an unrecognized command is sent to the ML243xA, an SRQ will be given. Send:
asdf
3. An SRQ will be indicated.
4. To clear the SRQ do a serial poll, this should return the decimal value 96, bit 6 for the
SRQ and bit 5 for the ESB. The SRQ will be cleared.
5. To read the Event Status Register (ESR), send:
*ESR?
6. This will put 32 (or 160 if PON is set) in the output buffer to be read.
Message Available Bit (MAV)
This bit is set if there is any data in the output buffer waiting to be read, and can be used to
ensure that only the latest reading is used. Upon receiving a request for data, the next
reading taken is put in the output buffer. The data in the output buffer should always be read
when data is available to ensure that old data is never left behind. The advantage of this
method is that if the MAV bit is not set, the controller can not read old data, therefore data
can only be read after it has been requested. Example:
1. In Readout display with the output buffer empty and the MAV bit not set, configure the
ML243xA to give an SRQ on data becoming available by setting bit 4 in the Status
Register Enable byte (SRE):
*SRE 16
2. Request data from display channel 1 by sending:
O 1
3. The SRQ will be set with the new reading which will now be in the output buffer ready
to be read. The data should now be read so that the MAV bit will be cleared. If the data
is not read, or the output buffer not cleared, and another request for data is made this
data will be buffered after the previous data.
OPC Operation Complete. When a program message that includes the *OPC
command has been completed, and the GPIB interface is idle, with any
responses read out of the output buffer this bit is set. For example, if the last
command in a configuration sequence is *OPC, the OPC bit in the event
status register will be set when that configuration list has been completed.
Table 8-4. Event Status Register (ESR)
Bit Description