ARM ARM7TDMI - Page 4

Contents
iv Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
Chapter 3 Memory Interface
3.1 About the memory interface ....................................................................... 3-2
3.2 Bus interface signals .................................................................................. 3-3
3.3 Bus cycle types .......................................................................................... 3-4
3.4 Addressing signals ................................................................................... 3-11
3.5 Address timing .......................................................................................... 3-14
3.6 Data timed signals .................................................................................... 3-17
3.7 Stretching access times ............................................................................ 3-29
3.8 Privileged mode access ............................................................................ 3-31
3.9 Reset sequence after power up ................................................................ 3-32
Chapter 4 Coprocessor Interface
4.1 About coprocessors .................................................................................... 4-2
4.2 Coprocessor interface signals .................................................................... 4-4
4.3 Pipeline following signals ............................................................................ 4-5
4.4 Coprocessor interface handshaking ........................................................... 4-6
4.5 Connecting coprocessors ......................................................................... 4-12
4.6 If you are not using an external coprocessor ............................................ 4-15
4.7 Undefined instructions .............................................................................. 4-16
4.8 Privileged instructions ............................................................................... 4-17
Chapter 5 Debug Interface
5.1 About the debug interface .......................................................................... 5-2
5.2 Debug systems ........................................................................................... 5-4
5.3 Debug interface signals .............................................................................. 5-7
5.4 ARM7TDMI core clock domains ............................................................... 5-11
5.5 Determining the core and system state .................................................... 5-13
5.6 About EmbeddedICE-RT logic ................................................................. 5-14
5.7 Disabling EmbeddedICE-RT .................................................................... 5-16
5.8 Debug Communications Channel ............................................................. 5-17
5.9 Monitor mode ............................................................................................ 5-21
Chapter 6 Instruction Cycle Timings
6.1 About the instruction cycle timing tables .................................................... 6-3
6.2 Branch and branch with link ....................................................................... 6-4
6.3 Thumb branch with link ............................................................................... 6-5
6.4 Branch and Exchange ................................................................................ 6-6
6.5 Data operations .......................................................................................... 6-7
6.6 Multiply and multiply accumulate ................................................................ 6-9
6.7 Load register ............................................................................................. 6-12
6.8 Store register ............................................................................................ 6-14
6.9 Load multiple registers ............................................................................. 6-15
6.10 Store multiple registers ............................................................................. 6-17
6.11 Data swap ................................................................................................. 6-18
6.12 Software interrupt and exception entry ..................................................... 6-19
6.13 Coprocessor data operation ..................................................................... 6-20